POWER MOSFET WITH REDUCED CURRENT LEAKAGE AND METHOD OF FABRICATING THE POWER MOSFET

    公开(公告)号:US20240379741A1

    公开(公告)日:2024-11-14

    申请号:US18779549

    申请日:2024-07-22

    Inventor: Yean Ching YONG

    Abstract: An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.

    EMBEDDED WAFER LEVEL OPTICAL SENSOR PACKAGING
    152.
    发明公开

    公开(公告)号:US20240282881A1

    公开(公告)日:2024-08-22

    申请号:US18649789

    申请日:2024-04-29

    Inventor: Jing-En LUAN

    CPC classification number: H01L31/12 H01L31/02005 H01L31/0203 H01L31/186

    Abstract: The present disclosure is directed to a sensor die with an embedded light sensor and an embedded light emitter as well as methods of manufacturing the same. The light emitter in the senor die is surrounded by a resin. The sensor die is incorporated into semiconductor device packages as well as methods of manufacturing the same. The semiconductor device packages include a first optically transmissive structure on the light sensor of the sensor die and a second optically transmissive structure on the light emitter of the sensor die. The first optically transmissive structure and the second optically transmissive structure cover and protect the light sensor and the light emitter, respectively. A molding compound is on a surface of a sensor die and covers sidewalls of the first and second optically transmissive structures on the sensor die.

    Wafer level chip scale package having varying thicknesses

    公开(公告)号:US11721657B2

    公开(公告)日:2023-08-08

    申请号:US16874392

    申请日:2020-05-14

    Inventor: Jing-En Luan

    CPC classification number: H01L24/14 H01L23/49816

    Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

    MOLDED PROXIMITY SENSOR
    159.
    发明申请

    公开(公告)号:US20230071048A1

    公开(公告)日:2023-03-09

    申请号:US18055138

    申请日:2022-11-14

    Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.

    Crack detection integrity check
    160.
    发明授权

    公开(公告)号:US11585847B2

    公开(公告)日:2023-02-21

    申请号:US17826705

    申请日:2022-05-27

    Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

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