公开(公告)号：US09401351B2

公开(公告)日：2016-07-26

申请号：US14610173

申请日：2015-01-30

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L27/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/102 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/74 ,  H01L29/7408 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/1301

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract translation: 电子器件包括具有阳极，阴极，设置在阳极侧的第一双极晶体管的晶闸管。 第二双极晶体管设置在阴极侧。 这两个双极晶体管被嵌套并连接在阳极和阴极之间。 MOS晶体管耦合在第二双极晶体管的集电极区域和发射极区域之间。 晶体管具有通过并入第二双极晶体管的基极区的至少一部分的电阻半导体区连接到阴极的栅极区。

公开(公告)号：US09391015B2

公开(公告)日：2016-07-12

申请号：US14079393

申请日：2013-11-13

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Simon Jeannot ,  Pascal Tannhof

IPC: H01L21/02 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

公开(公告)号：US09362380B2

公开(公告)日：2016-06-07

申请号：US14104993

申请日：2013-12-12

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/737 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, =; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract translation: 本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷， 以及通过在凹部中选择性地外延生长包含SiGe的膜来形成异质结双极晶体管的基极。

公开(公告)号：US09287254B2

公开(公告)日：2016-03-15

申请号：US14599167

申请日：2015-01-16

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat

IPC: H02H9/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/06 ,  H01L29/74 ,  H01L29/747

CPC classification number: H01L27/0248 ,  H01L27/0262 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/7436 ,  H01L29/747

Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.

Abstract translation: 电子设备包括第一设备终端和第二设备终端。 第一和第二晶闸管反向连接在两个器件端子之间。 第一和第二MOS晶体管分别耦合在两个晶闸管的两个NPN晶体管的导通电极（发射极和集电极）之间。 第三MOS晶体管耦合在两个晶闸管的两个NPN双极晶体管的发射极之间，第四个MOS晶体管耦合在两个晶闸管的两个PNP双极晶体管的基极之间。 栅极区域对于所有MOS晶体管是公共的，并且半导体衬底区域包括所有MOS晶体管的衬底。

公开(公告)号：US09270300B2

公开(公告)日：2016-02-23

申请号：US14177358

申请日：2014-02-11

Applicant: STMICROELECTRONICS S.A. ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE DE BORDEAUX

Inventor： Didier Belot ,  Yann Deval ,  Francois Rivet

IPC: H04B1/02 ,  H04B1/00 ,  H04B1/403 ,  H04L27/26 ,  H04B1/04

CPC classification number: H04B1/0021 ,  H04B1/0014 ,  H04B1/406 ,  H04B2001/0491 ,  H04L27/2639 ,  H04L27/2642

Abstract: A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies.

Abstract translation: 一种用于产生射频信号的方法，其中待传输的信号被分解成不同频率的周期性基本信号的加权和。

公开(公告)号：US09236478B2

公开(公告)日：2016-01-12

申请号：US14193833

申请日：2014-02-28

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Yves Morand ,  Romain Wacquez ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7856

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract translation: 一种从包括半导体载体的氧化硅层上的半导体层的SOI型结构制造鳍式MOS晶体管的方法，该方法包括以下步骤：a）从半导体层的表面形成至少一个 沟槽，限定半导体层中的至少一个翅片，并一直延伸到半导体支撑体的表面; b）蚀刻位于翅片下方的氧化硅层的一部分的侧面，以在翅片下方形成至少一个凹部; 以及c）用在氧化硅上可选择性地蚀刻的材料填充所述凹部。

公开(公告)号：US09147725B2

公开(公告)日：2015-09-29

申请号：US13935813

申请日：2013-07-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot

IPC: H01L49/02 ,  H01L27/02 ,  H01L27/08

CPC classification number: H01L28/92 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/91

Abstract: A semiconductor device includes a substrate wafer and having a front face and a back face. A front hole is formed in the front face and a multilayer capacitor is formed in the front hole. A back hole is formed in the back face of the substrate wafer to expose at least a portion of the multilayer capacitor. A front electrical connection on the front face and a back electrical connection in the back hole are used to make electrical connection to first and second conductive plates of the multilayer capacitor which are separated by a dielectric layer. The front hole may have a cylindrical shape or an annular shape.

Abstract translation: 半导体器件包括具有正面和背面的衬底晶片。 在前面形成有前孔，在前孔中形成有层叠电容器。 在基板晶片的背面形成有后孔，露出至少一部分多层电容器。 使用前表面上的前电连接和后孔中的背电连接来与层叠电容器的由电介质层隔开的第一和第二导电板电连接。 前孔可以具有圆柱形或环形。

公开(公告)号：US20150214214A1

公开(公告)日：2015-07-30

申请号：US14610173

申请日：2015-01-30

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0262 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/74 ,  H01L29/7408 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/1301

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract translation: 电子器件包括具有阳极，阴极，设置在阳极侧的第一双极晶体管的晶闸管。 第二双极晶体管设置在阴极侧。 这两个双极晶体管被嵌套并连接在阳极和阴极之间。 MOS晶体管耦合在第二双极晶体管的集电极区域和发射极区域之间。 晶体管具有通过并入第二双极晶体管的基极区的至少一部分的电阻半导体区连接到阴极的栅极区。

公开(公告)号：US09008603B2

公开(公告)日：2015-04-14

申请号：US13707736

申请日：2012-12-07

Applicant: STMicroelectronics S.A.

Inventor： Floria Blanchet ,  Christophe Arricastres ,  Denis Pache

IPC: H04B1/10 ,  H01F5/00 ,  H01F30/04 ,  H01L23/522 ,  H01L27/01 ,  H01L49/02 ,  H03H7/42 ,  H01P5/10 ,  H01L23/66 ,  H03H7/01

CPC classification number: H01F5/003 ,  H01F21/12 ,  H01F27/2804 ,  H01F30/04 ,  H01L23/5227 ,  H01L23/66 ,  H01L27/01 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01P5/10 ,  H03H7/1775 ,  H03H7/42 ,  H01L2924/00

Abstract: An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

Abstract translation: 集成电路包括具有N个通道的平衡不平衡型的集成变压器，其中N大于2.集成变压器在衬底上包括相互感应耦合并且分别与N个通道相关联的N个感应电路 。

公开(公告)号：US09007848B2

公开(公告)日：2015-04-14

申请号：US13754427

申请日：2013-01-30

Applicant: STMicroelectronics S.A.

Inventor： Anis Feki

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

CPC classification number: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

Abstract translation: 易失性存储器包括执行数据写入和读取操作的易失性存储器单元。 存储单元以行和列排列并且分布在每列的第一分离的存储单元组中。 对于每列，存储器包括专用于写操作并连接到列的所有存储器单元的写位线，以及专用于读操作的读位线。 每个读位线连接到第一组存储器单元之一的所有存储单元。 列中的每个存储单元连接到单个读取位线。