公开(公告)号：US08704358B2

公开(公告)日：2014-04-22

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L23/04

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10μm，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连电平的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US09385424B2

公开(公告)日：2016-07-05

申请号：US13920237

申请日：2013-06-18

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-François Carpentier

IPC: H01Q1/50 ,  H01L23/66 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: The three-dimensional integrated structure including a support element, an interface device connected to the support element by first electrically conductive connection, an integrated circuit arranged between the support element and the interface device and connected to the interface device by second electrically conductive connection, a filler region between the second electrically conductive connection and between the interface device and the integrated circuit, and an antenna, having a radiating element in electromagnetic coupling with an excitation element through the interconnection of a slot, the antenna being distributed over the interface device and the integrated circuit.

Abstract translation: 三维一体化结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，布置在支撑元件和接口装置之间并通过第二导电连接连接到接口装置的集成电路， 所述第二导电连接之间和所述接口装置与所述集成电路之间的填充区域，以及天线，所述天线具有通过所述插槽的互连与激励元件电磁耦合的辐射元件，所述天线分布在所述接口装置上， 集成电路。

公开(公告)号：US20130335297A1

公开(公告)日：2013-12-19

申请号：US13920237

申请日：2013-06-18

Applicant: Commissariat à I'Ènergie Atomique et aux 'Ènergies Alternatives ,  STMicroelectronics S.A.

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-François Carpentier

IPC: H01Q1/50

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: The three-dimensional integrated structure including a support element, an interface device connected to the support element by first electrically conductive connection, an integrated circuit arranged between the support element and the interface device and connected to the interface device by second electrically conductive connection, a filler region between the second electrically conductive connection and between the interface device and the integrated circuit, and an antenna, having a radiating element in electromagnetic coupling with an excitation element through the interconnection of a slot, the antenna being distributed over the interface device and the integrated circuit.

Abstract translation: 三维一体化结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，布置在支撑元件和接口装置之间并通过第二导电连接连接到接口装置的集成电路， 所述第二导电连接之间和所述接口装置与所述集成电路之间的填充区域，以及天线，所述天线具有通过所述插槽的互连与激励元件电磁耦合的辐射元件，所述天线分布在所述接口装置上， 集成电路。

公开(公告)号：US20130140693A1

公开(公告)日：2013-06-06

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10um，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连层的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US09147725B2

公开(公告)日：2015-09-29

申请号：US13935813

申请日：2013-07-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot

IPC: H01L49/02 ,  H01L27/02 ,  H01L27/08

CPC classification number: H01L28/92 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/91

Abstract: A semiconductor device includes a substrate wafer and having a front face and a back face. A front hole is formed in the front face and a multilayer capacitor is formed in the front hole. A back hole is formed in the back face of the substrate wafer to expose at least a portion of the multilayer capacitor. A front electrical connection on the front face and a back electrical connection in the back hole are used to make electrical connection to first and second conductive plates of the multilayer capacitor which are separated by a dielectric layer. The front hole may have a cylindrical shape or an annular shape.

Abstract translation: 半导体器件包括具有正面和背面的衬底晶片。 在前面形成有前孔，在前孔中形成有层叠电容器。 在基板晶片的背面形成有后孔，露出至少一部分多层电容器。 使用前表面上的前电连接和后孔中的背电连接来与层叠电容器的由电介质层隔开的第一和第二导电板电连接。 前孔可以具有圆柱形或环形。

公开(公告)号：US20140015102A1

公开(公告)日：2014-01-16

申请号：US13935813

申请日：2013-07-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/91

Abstract: A semiconductor device includes a substrate wafer and having a front face and a back face. A front hole is formed in the front face and a multilayer capacitor is formed in the front hole. A back hole is formed in the back face of the substrate wafer to expose at least a portion of the multilayer capacitor. A front electrical connection on the front face and a back electrical connection in the back hole are used to make electrical connection to first and second conductive plates of the multilayer capacitor which are separated by a dielectric layer. The front hole may have a cylindrical shape or an annular shape.

Abstract translation: 半导体器件包括具有正面和背面的衬底晶片。 在前面形成有前孔，在前孔中形成有层叠电容器。 在基板晶片的背面形成有后孔，露出至少一部分多层电容器。 使用前表面上的前电连接和后孔中的背电连接来与层叠电容器的由电介质层隔开的第一和第二导电板电连接。 前孔可以具有圆柱形或环形。