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公开(公告)号：US20230395113A1
公开(公告)日：2023-12-07
申请号：US18203877
申请日：2023-05-31
Applicant: Micron Technology, Inc.
Inventor： Giorgio Servalli , Marcello Mariani , Agostino Pirovano
CPC classification number: G11C11/2253 , G11C11/221 , H01L29/516 , H10B53/10 , H10B53/20 , G11C5/063
Abstract: Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.
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公开(公告)号：US11696454B2
公开(公告)日：2023-07-04
申请号：US17306444
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Russell L. Meyer , Agostino Pirovano , Lorenzo Fratin
CPC classification number: H10B63/845 , G11C13/003 , G11C13/004 , G11C13/0069 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/823 , H10N70/841 , H10N70/8828 , G11C13/0004 , G11C2213/71
Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
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公开(公告)号：US11482280B2
公开(公告)日：2022-10-25
申请号：US16436734
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US11475951B2
公开(公告)日：2022-10-18
申请号：US17162563
申请日：2021-01-29
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory with reduced program voltages. An example apparatus can include an array of memory cells that further includes a first memory cell coupled to a first access line and to a first one of a plurality of second access lines and a second memory cell coupled to the first access line and to a second one of the plurality of second access lines. The circuitry can be configured to apply, across the second memory cell, a first voltage differential having a first polarity and a first magnitude. The first voltage differential reduces, if the second memory cell is programmed to a first data state, a magnitude of a drifted threshold voltage for programming the second memory cell to a second data state. The circuitry is further configured to apply, subsequent to the application of the first voltage differential, a first signal to the first access line. The circuitry is further configured to, while the first signal is being applied to the first access line, apply, subsequent to the application of the first voltage differential, a second voltage differential having a second polarity and the first magnitude across the first memory cell and apply a third voltage differential having the second polarity across the second memory cell. A material implication operation is performed as a result of the first, second, and third voltage differentials applied across the first and the second memory cells with a result of the material implication operation being stored on the second memory cell.
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公开(公告)号：US20220310195A1
公开(公告)日：2022-09-29
申请号：US17609577
申请日：2020-10-13
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano
Abstract: Methods, systems, and devices related to 3D self-selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, including: applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array, and adopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on the at least three selected word lines of the memory array.
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Patent Agency Ranking
公开(公告)号：US20220301619A1
公开(公告)日：2022-09-22
申请号：US17716740
申请日：2022-04-08
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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公开(公告)号：US11302390B2
公开(公告)日：2022-04-12
申请号：US16926557
申请日：2020-07-10
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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公开(公告)号：US20220059763A1
公开(公告)日：2022-02-24
申请号：US17480694
申请日：2021-09-21
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US11217322B2
公开(公告)日：2022-01-04
申请号：US16990114
申请日：2020-08-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US11200950B2
公开(公告)日：2021-12-14
申请号：US16518847
申请日：2019-07-22
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
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