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公开(公告)号：US11175979B2
公开(公告)日：2021-11-16
申请号：US16533328
申请日：2019-08-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vamsi Pavan Rayaprolu , Harish R. Singidi , Kishore Kumar Muchherla , Ashutosh Malshe , Xiangang Luo
IPC: G06F11/07
Abstract: A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.
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公开(公告)号：US11132044B2
公开(公告)日：2021-09-28
申请号：US16406779
申请日：2019-05-08
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Xiangang Luo , Ting Luo , Jianmin Huang
IPC: G06F1/3206 , G06F12/06 , G06F12/02 , G06F1/3296
Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.
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公开(公告)号：US11074989B2
公开(公告)日：2021-07-27
申请号：US16079737
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Jianmin Huang , Deping He , Xiangang Luo , Harish Reddy Singidi , Kulachet Tanpairoj , John Zhang , Ting Luo
Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.
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公开(公告)号：US10983829B2
公开(公告)日：2021-04-20
申请号：US16510526
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Jianmin Huang
Abstract: Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.
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公开(公告)号：US10931307B2
公开(公告)日：2021-02-23
申请号：US16235171
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Ting Luo
Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.
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Patent Agency Ranking
公开(公告)号：US10915395B2
公开(公告)日：2021-02-09
申请号：US16193171
申请日：2018-11-16
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Kishore Kumar Muchherla , Harish Reddy Singidi , Xiangang Luo , Renato Padilla, Jr. , Gary F. Besinga , Sampath Ratnam , Vamsi Pavan Rayaprolu
Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.
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公开(公告)号：US20210012851A1
公开(公告)日：2021-01-14
申请号：US16079737
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Jianmin Huang , Deping He , Xiangang Luo , Harish Reddy Singidi , Kulache Tanpairoj , John Zhang , Ting Luo
Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.
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公开(公告)号：US20200371870A1
公开(公告)日：2020-11-26
申请号：US16989478
申请日：2020-08-10
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Ravaprolu , Ashutosh Malshe
Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US20200159447A1
公开(公告)日：2020-05-21
申请号：US16193171
申请日：2018-11-16
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Kishore Kumar Muchherla , Harish Reddy Singidi , Xiangang Luo , Renato Padilla, JR. , Gary F. Besinga , Sampath Ratnam , Vamsi Pavan Rayaprolu
Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.
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公开(公告)号：US20200110661A1
公开(公告)日：2020-04-09
申请号：US16155573
申请日：2018-10-09
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Xiangang Luo , Preston Thomson , Michael G. McNeeley
Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.
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