公开(公告)号：US20230402105A1

公开(公告)日：2023-12-14

申请号：US17837744

申请日：2022-06-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08

Abstract: The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read.

公开(公告)号：US11823744B2

公开(公告)日：2023-11-21

申请号：US17487634

申请日：2021-09-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C11/34 ,  G11C16/22 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/22 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.

公开(公告)号：US11776643B2

公开(公告)日：2023-10-03

申请号：US17337758

申请日：2021-06-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/16 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks. In this manner, the same programming voltage is applied to planes in a multi-plane programming operation, and the existing blocks receive a relatively lower gate-to-channel voltage, while the new block(s) receive a relatively higher gate-to-channel voltage.

公开(公告)号：US20230307070A1

公开(公告)日：2023-09-28

申请号：US17666940

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11556

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.

公开(公告)号：US20230290419A1

公开(公告)日：2023-09-14

申请号：US17690713

申请日：2022-03-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Takayuki Inoue ,  Jiacen Guo

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30

Abstract: The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the bit lines during each of the three programming pulses. The patterns include two pre-established patterns and additional patterns that are derived from the pre-established patterns using logic operations.

公开(公告)号：US20230282288A1

公开(公告)日：2023-09-07

申请号：US17685613

申请日：2022-03-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Ohwon Kwon ,  James Kai ,  Yuki Mizutani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24

Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read operations, this allows the memory device to operate with lower power requirements.

公开(公告)号：US20230154538A1

公开(公告)日：2023-05-18

申请号：US17527747

申请日：2021-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Fanqi Wu ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/3427 ,  G11C11/5671

Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.

公开(公告)号：US20230053269A1

公开(公告)日：2023-02-16

申请号：US17403310

申请日：2021-08-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higanshitani ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

Abstract: A storage device that includes a non-volatile memory with a control circuitry is provided. The control circuitry is communicatively coupled to a memory block that includes an array of memory cells. The control circuitry is configured to program one or more bits of data into the memory cells. The control circuitry is further configured to operate the non-volatile memory in a multi-bit per memory cell mode, monitor a usage metric while the non-volatile memory is operating in the multi-bit per memory cell mode, and determine if the usage metric has crossed a predetermined threshold. In response to the usage metric not crossing the predetermined threshold, the control circuitry continues to operate the non-volatile memory in the multi-bit per memory cell mode. In response to the usage metric crossing the predetermined threshold, the control circuitry automatically operates the non-volatile memory in a single-bit per memory cell mode.

公开(公告)号：US20230046677A1

公开(公告)日：2023-02-16

申请号：US17398718

申请日：2021-08-10

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Shubhajit Mukherjee

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

公开(公告)号：US20230041476A1

公开(公告)日：2023-02-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.