公开(公告)号：US20190051731A1

公开(公告)日：2019-02-14

申请号：US15691717

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/08

Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

公开(公告)号：US20190043861A1

公开(公告)日：2019-02-07

申请号：US16149125

申请日：2018-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/2256 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823892 ,  H01L27/0886 ,  H01L29/66803

Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

公开(公告)号：US20190027588A1

公开(公告)日：2019-01-24

申请号：US15675380

申请日：2017-08-11

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3115

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dopping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion. The recessed portion is located between the fin portions. The bottom surface of the recessed portion is lower than the surface of the substrate between the fin portions. The dopping layer is disposed on the sidewall of the fin portions, the surface of the substrate, and the sidewall and the bottom portion of the recessed portion. The dielectric layer is disposed on the dopping layer. The top surface of the dopping layer and the top surface of the dielectric layer are lower than the top surface of each of the fin portions.

公开(公告)号：US20190013381A1

公开(公告)日：2019-01-10

申请号：US15656802

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Ching-Ling Lin

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

公开(公告)号：US10164039B2

公开(公告)日：2018-12-25

申请号：US15283445

申请日：2016-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L21/768

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

公开(公告)号：US10134629B1

公开(公告)日：2018-11-20

申请号：US15696267

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  En-Chiuan Liou ,  Chih-Wei Yang

IPC: H01L21/44 ,  H01L21/768 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535

Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.

公开(公告)号：US20180301336A1

公开(公告)日：2018-10-18

申请号：US15489842

申请日：2017-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/76224 ,  H01L29/66795

Abstract: A method of pattern transfer is provided, comprising: providing a target layer; forming a first pattern above the target layer; forming a second pattern (such as spacer loops) above the target layer and above the first pattern, wherein one closed end of the second pattern partially overlaps with the first pattern; and transferring the second pattern to the target layer, wherein the first pattern stops transferring pattern of the closed end of the second pattern to the target layer.

公开(公告)号：US20180239235A1

公开(公告)日：2018-08-23

申请号：US15481479

申请日：2017-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/24 ,  G03F1/22

Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.

公开(公告)号：US20180233419A1

公开(公告)日：2018-08-16

申请号：US15495942

申请日：2017-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/66 ,  H01L23/544

CPC classification number: H01L22/12 ,  G03F7/70633 ,  G03F7/70683 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

公开(公告)号：US10043807B1

公开(公告)日：2018-08-07

申请号：US15641236

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Cheng Tung ,  Chun-Tsen Lu ,  En-Chiuan Liou ,  Kuan-Hung Chen

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.