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公开(公告)号：US20230194787A1
公开(公告)日：2023-06-22
申请号：US18167392
申请日：2023-02-10
发明人： Frédéric BOEUF , Luca Maggi
CPC分类号： G02B6/124 , G02B6/34 , G02B6/43 , G02B6/30 , G02B6/12004 , G02B6/136 , G02B2006/12061
摘要： A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
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公开(公告)号：US20230187425A1
公开(公告)日：2023-06-15
申请号：US18147563
申请日：2022-12-28
IPC分类号： H01L25/16 , H01L21/762 , H01L21/763 , H01L25/00
CPC分类号： H01L25/16 , H01L21/763 , H01L21/76224 , H01L25/50
摘要： A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.
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公开(公告)号：US11676434B2
公开(公告)日：2023-06-13
申请号：US17198612
申请日：2021-03-11
发明人： Carlo Cimino , Luca Di Cosmo
CPC分类号： G07C9/22 , G06F21/35 , G07C9/00174 , G07C9/00309 , G06F2221/2103 , G06F2221/2111 , G07C2009/00341 , G07C2009/00769 , H04W4/80
摘要： A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.
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公开(公告)号：US11675720B2
公开(公告)日：2023-06-13
申请号：US17811209
申请日：2022-07-07
IPC分类号： G06F13/28 , G06F9/46 , G06F13/37 , G06F13/372 , G06F17/14
CPC分类号： G06F13/287 , G06F9/467 , G06F13/37 , G06F13/372 , G06F17/142
摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
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155.发明授权公开(公告)号：US11673799B2
公开(公告)日：2023-06-13
申请号：US17155429
申请日：2021-01-22
CPC分类号： B81C1/00158 , H01L41/35 , B81C2201/013
摘要： To manufacture an oscillating structure, a wafer is processed by: forming torsional elastic elements; forming a mobile element connected to the torsional elastic elements; processing the first side of the wafer to form a mechanical reinforcement structure; and processing the second side of said wafer by steps of chemical etching, deposition of metal material, and/or deposition of piezoelectric material. Processing of the first side of the wafer is carried out prior to processing of the second side of the wafer so as not to damage possible sensitive structures formed on the first side of the wafer.
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公开(公告)号：US20230179244A1
公开(公告)日：2023-06-08
申请号：US17457496
申请日：2021-12-03
CPC分类号： H04B1/16 , H03F3/19 , H04L27/06 , H03F2200/451
摘要： A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelop detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.
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157.发明授权公开(公告)号：US11670685B2
公开(公告)日：2023-06-06
申请号：US17226003
申请日：2021-04-08
发明人： Simone Rascuná , Paolo Badalá , Anna Bassi , Gabriele Bellocchi
IPC分类号： H01L29/872 , H01L29/16 , H01L29/66
CPC分类号： H01L29/1608 , H01L29/1606 , H01L29/6603 , H01L29/66143 , H01L29/872
摘要： A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.
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公开(公告)号：US11669770B2
公开(公告)日：2023-06-06
申请号：US16203275
申请日：2018-11-28
IPC分类号： G06N20/00 , G01C19/00 , G01P15/00 , G06F3/0346
CPC分类号： G06N20/00 , G01C19/00 , G01P15/00 , G06F3/0346 , G06F2218/02 , G06F2218/08 , G06F2218/12
摘要： Technological advancements are disclosed that utilize inertial sensor data associated with a device to determine a new feature array and if the new feature array is within an existing class within a state space associated with the inertial sensor data. In response to the new feature array being included in the existing class, the new feature array is added to the existing class and a representation of the existing class in the state space is updated based on the new feature array and an existing representation of the existing class. In response to the new feature array not being included in the existing class, a new class is created based on the new feature array.
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公开(公告)号：US11668585B2
公开(公告)日：2023-06-06
申请号：US17460030
申请日：2021-08-27
发明人： Luca Guerinoni , Gabriele Gattere
CPC分类号： G01C25/005 , G01C19/726
摘要： A gyroscopic sensor unit detects a phase drift between a demodulated output signal and demodulation signal during output of a quadrature test signal. A delay calculator detects the phase drift based on changes in the demodulated output signal during application of the quadrature test signal. A delay compensation circuit compensates for the phase drift by delaying the demodulation signal by the phase drift value.
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160.发明公开公开(公告)号：US20230170803A1
公开(公告)日：2023-06-01
申请号：US18154167
申请日：2023-01-13
发明人： Enrico Ferrara , Luca Morinelli
CPC分类号： H02M3/158 , H02M1/08 , H02M3/1566 , H02M1/0019
摘要： An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.
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