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公开(公告)号：US20230047409A1
公开(公告)日：2023-02-16
申请号：US17401702
申请日：2021-08-13
Applicant: STMicroelectronics International N.V.
Inventor： Kamaldeep Bansal , Alok Kumar Mittal , Jitendra Jain
Abstract: A method to provision a node network including provisioning a first generation of nodes by a root node; and provisioning a second generation of nodes by the first generation of nodes. Wherein at least one node from the first generation of nodes or the second generation of nodes is provisioned simultaneously with at least one other node from the first generation of nodes or the second generation of nodes.
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公开(公告)号：US20230042541A1
公开(公告)日：2023-02-09
申请号：US17443556
申请日：2021-07-27
Applicant: STMicroelectronics International N.V.
Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.
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公开(公告)号：US20230024278A1
公开(公告)日：2023-01-26
申请号：US17860959
申请日：2022-07-08
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Sharad Gupta
IPC: G01R31/40
Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.
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公开(公告)号：US20230022608A1
公开(公告)日：2023-01-26
申请号：US17383547
申请日：2021-07-23
Applicant: STMicroelectronics International N.V.
Inventor： Subodh Vikram SHUKLA , Saurabh SONA
Abstract: Described herein is an electric motor drive system, including at least one power phase line, an external controller configured to generate a drive signal and provide the drive signal to the at least one power phase line, and motor electronics. The motor electronics include at least one switch coupled between the at least one power phase line and at least one electric motor terminal, and an internal controller configured to cooperate with the external controller to perform an authentication process therebetween. The external controller is further configured to cause the at least one switch to electrically couple the at least one power phase line to the at least one electric motor terminal in response to success of the authentication process.
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公开(公告)号：US11563436B2
公开(公告)日：2023-01-24
申请号：US17863708
申请日：2022-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
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Patent Agency Ranking
公开(公告)号：US20230009329A1
公开(公告)日：2023-01-12
申请号：US17850207
申请日：2022-06-27
Applicant: STMicroelectronics International N.V.
Inventor： Harsh RAWAT , Kedar Janardan DHORI , Promod KUMAR , Nitin CHAWLA , Manuj AYODHYAWASI
IPC: G11C11/408 , G11C11/4094 , G11C11/4074 , G11C11/4096
Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.
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公开(公告)号：US20230008833A1
公开(公告)日：2023-01-12
申请号：US17849903
申请日：2022-06-27
Applicant: STMicroelectronics International N.V.
Inventor： Harsh RAWAT , Kedar Janardan DHORI , Promod KUMAR , Nitin CHAWLA , Manuj AYODHYAWASI
IPC: G11C11/418
Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.
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公开(公告)号：US11550348B2
公开(公告)日：2023-01-10
申请号：US17211545
申请日：2021-03-24
Applicant: STMicroelectronics International N.V.
Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.
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公开(公告)号：US20230006679A1
公开(公告)日：2023-01-05
申请号：US17931043
申请日：2022-09-09
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Prashutosh GUPTA , Ankit GUPTA
Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.
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160.发明授权公开(公告)号：US11522446B2
公开(公告)日：2022-12-06
申请号：US17494244
申请日：2021-10-05
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.
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