Flat display screen with an addressing memory
    151.
    发明授权
    Flat display screen with an addressing memory 失效
    具有寻址存储器的平面显示屏

    公开(公告)号:US06713970B2

    公开(公告)日:2004-03-30

    申请号:US09858813

    申请日:2001-05-16

    Applicant: Bernard Bancal

    Inventor: Bernard Bancal

    CPC classification number: G09G3/22 H01J3/022 H01J2201/319 H01J2329/00

    Abstract: A cathode-grid plate of a field-effect flat display screen of the type including a first set of row conductors, a second set of column conductors and, for each screen pixel, defined by the intersection of a column and of a line, an element for temporarily storing the luminance control signal of the considered pixel.

    Abstract translation: 场效应平面显示屏的阴极栅格板,其类型包括第一组行导体,第二组列导体,并且对于每个屏幕像素,由一列和一条线的交点定义, 元素,用于临时存储所考虑的像素的亮度控制信号。

    Nitrogen and phosphorus doped amorphous silicon as resistor for field emission display device baseplate
    152.
    发明申请
    Nitrogen and phosphorus doped amorphous silicon as resistor for field emission display device baseplate 失效
    氮和磷掺杂的非晶硅作为场致发射显示器件基板的电阻器

    公开(公告)号:US20040036399A1

    公开(公告)日:2004-02-26

    申请号:US10644443

    申请日:2003-08-19

    Abstract: Described herein is a resistor layer for use in field emission display devices and the like, and its method of manufacture. The resistor layer is an amorphous silicon layer doped with nitrogen and phosphorus. Nitrogen concentration in the resistor layer is preferably between about 5 and 15 atomic percent. The presence of nitrogen and phosphorus in the silicon prevents diffusion of Si atoms into metal conductive layers such as aluminum, even up to diffusion and packaging temperatures. The nitrogen and phosphorus also prevent defects from forming at the boundary between the resistor layer and metal conductor. This leads to better control over shorting and improved resistivity in the resistor.

    Abstract translation: 这里描述的是用于场发射显示装置等的电阻层及其制造方法。 电阻层是掺杂有氮和磷的非晶硅层。 电阻层中的氮浓度优选为约5至15原子%。 硅中的氮和磷的存在防止Si原子扩散到金属导电层如铝中,甚至达到扩散和封装温度。 氮和磷还可以防止在电阻层和金属导体之间的边界处形成缺陷。 这导致更好地控制电阻器的短路和改善电阻率。

    Enhanced electron field emitter spindt tip and method for fabricating enhanced spindt tips

    公开(公告)号:US20030067258A1

    公开(公告)日:2003-04-10

    申请号:US09972430

    申请日:2001-10-05

    Inventor: Arthur Piehl

    CPC classification number: H01J9/025 H01J3/022 H01J2201/319

    Abstract: An enhanced Spindt-tip field emitter tip and a method for producing the enhanced Spindt-tip field emitter. A thin-film resistive heating element is positioned below the field emitter tip to allow for resistive heating of the tip in order to sharpen the tip and to remove adsorbed contaminants from the surface of the tip. Metal layers of the enhanced field emission device are separated by relatively thick dielectric bilayers, with the metal layers having increased thickness in the proximity of a cylindrical well in which the field emitter tip is deposited. Dielectric material is pulled back from the cylindrical aperture into which the field emitter tip is deposited in order to decrease buildup of conductive contaminants and the possibility of short circuits between metallic layers.

    Field effect transistors, field emission apparatuses, and a thin film transistor
    158.
    发明授权
    Field effect transistors, field emission apparatuses, and a thin film transistor 有权
    场效应晶体管,场发射装置和薄膜晶体管

    公开(公告)号:US06504170B1

    公开(公告)日:2003-01-07

    申请号:US09678468

    申请日:2000-10-02

    CPC classification number: H01L29/78618 H01J9/025 H01J2201/319

    Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device, includes a transistor configured to control the emission of electrons from an emitter.

    Abstract translation: 本发明包括场效应晶体管,场发射装置,薄膜​​晶体管和形成场效应晶体管的方法。 根据一个实施例,场效应晶体管包括被配置为形成沟道区的半导体层; 一对间隔导电掺杂的半导体区域,与半导体层的沟道区域电连接; 半导体区域中间的栅极; 以及在所述半导体层和所述栅极之间的栅极电介质层,所述栅极介电层被配置为使所述栅极与所述半导体层的沟道区域对准。 在一个方面,化学机械抛光使栅极与沟道区域自对准。 根据另一方面,场致发射器件包括被配置为控制来自发射极的电子的发射的晶体管。

    Integrally fabricated gated pixel elements and control circuitry for flat-panel displays
    159.
    发明授权
    Integrally fabricated gated pixel elements and control circuitry for flat-panel displays 失效
    整体制作的门控像素元件和平板显示器的控制电路

    公开(公告)号:US06492966B1

    公开(公告)日:2002-12-10

    申请号:US08281912

    申请日:1994-07-27

    CPC classification number: H01J1/3042 H01J2201/30403 H01J2201/319

    Abstract: Triode pixel devices and complementary triode logic devices for control of the pixel devices are disclosed. The pixel and logic devices are integrally fabricated in arrays suitable for full color flat display panels. Both pixel and logic elements are operated in a gate controlled avalanche mode. Pixel elements are formed from organic or inorganic electroluminescent (EL) materials ohmically contacted by low work function metal. The depletion region necessary for controlling EL intensity or preventing EL avalanche is affected by potentials to a gate element injected into the EL material. The shape of the gate element multiplies the field produced by the gate potential. Luminescence is directly viewed from the brighter, lateral EL emission not available in the prior art. The complementary logic devices are formed from separate depositions of n-type and p-type silicon with their respective gates connected in common. A manufacturing process to produce economical full color, large area, flat-panel, displays of high pixel density and redundancy is described. Small area high pixel density displays suitable for head-mounted military, avionic, and virtual reality display products are also discussed.

    Abstract translation: 公开了用于控制像素装置的三极体像素装置和互补三极管逻辑装置。 像素和逻辑器件被整体地制成阵列,适用于全彩平板显示面板。 像素和逻辑元件都以栅极控制的雪崩模式工作。 像素元件由低功函数金属欧姆接触的有机或无机电致发光(EL)材料形成。 用于控制EL强度或防止EL雪崩所需的耗尽区受到注入到EL材料中的栅极元件的电位的影响。 栅极元件的形状将由栅极电位产生的场相乘。 从现有技术中不可获得的较亮的侧向EL发射中直接观察发光。 互补逻辑器件由n型和p型硅的分开沉积形成,其相应的栅极共同连接。 描述了生产经济的全彩色,大面积,平板,高像素密度和冗余的显示器的制造工艺。 还讨论了适用于头戴式军用,航空电子和虚拟现实显示产品的小面积高像素密度显示器。

    Field emission device
    160.
    发明授权
    Field emission device 失效
    场发射装置

    公开(公告)号:US06456014B1

    公开(公告)日:2002-09-24

    申请号:US09606013

    申请日:2000-06-29

    CPC classification number: H01J1/304 H01J2201/319

    Abstract: A field emission device comprises an anode plate, an emitter plate having a plurality of filed emission portions that face the anode plate, and a gate plate having openings corresponding to the filed emission portions. The field emission device also comprises a current limiting element composed of a J FET or a MOSFET that is integrally formed with the gate plate and that is inserted between the gate plate and a gate voltage supply terminal. The loss caused by the emitter current is small as the current limiting element is inserted into a gate input portion. If the field emission device including a number of blocks each having the above structure is constituted, a power switching device having sufficient redundancy against a short circuit between the gate and the emitter can be implemented.

    Abstract translation: 场发射装置包括阳极板,具有面向阳极板的多个场发射部分的发射极板以及具有对应于场发射部分的开口的栅极板。 励磁发射装置还包括由与栅极板一体形成并且插入在栅极板和栅极电压提供端子之间的J FET或MOSFET组成的限流元件。 由于限流元件被插入到栅极输入部分中,由发射极电流引起的损耗很小。 如果构成包括多个具有上述结构的块的场发射器件,则可以实现具有足够的冗余以抵抗栅极和发射极之间的短路的功率开关器件。

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