公开(公告)号：US06873421B2

公开(公告)日：2005-03-29

申请号：US10181679

申请日：2001-10-31

Applicant: Ssang-Gun Lim ,  Seung-Woo Kim ,  Sang-Yoon Lee ,  Chang-Jin Chung ,  Yi-Bae Choi ,  Young-Sik Cho ,  Kyung-Keun Park

Inventor： Ssang-Gun Lim ,  Seung-Woo Kim ,  Sang-Yoon Lee ,  Chang-Jin Chung ,  Yi-Bae Choi ,  Young-Sik Cho ,  Kyung-Keun Park

IPC: H04N13/00 ,  G01B11/25 ,  G01B11/24

CPC classification number: G01B11/2527

Abstract: An apparatus and method for measuring a three-dimensional shape of an object using a projection moiré device. The method comprises the steps of obtaining a grid pattern image projected on a reference plane of a moving table and applying a buckets algorithm thereto, thereby achieving a reference phase, obtaining a grid pattern image projected on the object set on the moving table and applying a buckets algorithm thereto, thereby achieving an object phase, calculating a difference phase between the object phase and the reference phase, thereby achieving a moiré phase, and unwrapping the moiré phase, thereby achieving a level information of the object. The apparatus and method measure the three-dimensional shape using a projection grid without a reference grid, thereby achieving compactness of equipment, simplicity in usage and manufacturing cost reduction.

Abstract translation: 一种使用投影莫尔装置测量物体的三维形状的装置和方法。 该方法包括以下步骤：获得投影在移动台的参考平面上的网格图案图像并对其施加桶算法，从而实现参考相位，获得投影在移动台上的对象上的网格图案图像， 从而实现物体相位，计算物体相位与参考相位之间的差分相位，从而实现莫尔相位，并且展开莫尔相位，从而实现物体的等级信息。 该装置和方法使用没有参考网格的投影网格来测量三维形状，从而实现设备的紧凑性，使用简单性和制造成本降低。

公开(公告)号：US06686902B2

公开(公告)日：2004-02-03

申请号：US09804566

申请日：2001-03-12

Applicant: Sang-Yoon Lee

Inventor： Sang-Yoon Lee

IPC: G09G508

CPC classification number: G06F3/0236

Abstract: A method and apparatus for minimizing the number of key pressings required for character input. When a key is initially pressed, a controller searches, in a storage unit, for characters corresponding to the keys pressed, and sequentially displays the characters in a current cursor position according to a predetermined time that the key is pressed. When pressing of the key is terminated, the character presently displayed in the current cursor position is maintained and the cursor moves to the next cursor position. Since the wanted character can be inputted by pressing only one key, there is a minimal amount of keys utilized to input a character. In particular, by utilizing a consecutive input, the same character can be inputted more effectively and conveniently.

Abstract translation: 一种用于最小化字符输入所需的按键数量的方法和装置。 当初始按下键时，控制器在存储单元中搜索与按下的按键相对应的字符，并根据按下该键的预定时间顺序显示当前光标位置中的字符。 当按下键时，保持目前在当前光标位置显示的字符，光标移动到下一个光标位置。 由于可以通过仅按一个键来输入所需的字符，所以输入字符的键的数量最少。 特别地，通过利用连续输入，可以更有效和方便地输入相同的字符。

公开(公告)号：US08873131B2

公开(公告)日：2014-10-28

申请号：US13533353

申请日：2012-06-26

Applicant: Seung-hoon Han ,  Wan-joo Maeng ,  Sang-yoon Lee ,  Hong-seok Lee

Inventor： Seung-hoon Han ,  Wan-joo Maeng ,  Sang-yoon Lee ,  Hong-seok Lee

IPC: G02F1/33 ,  G02F1/00

CPC classification number: G02F1/33 ,  G01N29/2418 ,  G01N29/34 ,  G02F1/0072 ,  G02F2202/32 ,  G02F2203/10 ,  G03H1/2294 ,  G03H2001/0224 ,  G03H2225/21

Abstract: An acousto-optic device includes an acousto-optic medium having a multi-layer nanostructure; and a sonic wave generator configured to apply sonic waves to the acousto-optic medium having the multi-layer nanostructure. The acousto-optic medium having the multi-layer nanostructure includes a second layer formed of at least two materials that have different dielectric constants and alternate with each other; and a first layer disposed on a first surface of the second layer and formed of a first material, and/or a third layer disposed on a second surface of the second layer and formed of a fourth material.

Abstract translation: 声光装置包括具有多层纳米结构的声光介质; 以及声波发生器，被配置为将声波施加到具有多层纳米结构的声光介质。 具有多层纳米结构的声光介质包括由至少两种具有不同介电常数且彼此交替的材料形成的第二层; 以及设置在第二层的第一表面上并由第一材料形成的第一层和/或设置在第二层的第二表面上并由第四材料形成的第三层。

公开(公告)号：US08866136B2

公开(公告)日：2014-10-21

申请号：US12805379

申请日：2010-07-28

Applicant: Ji-sim Jung ,  Chang-seung Lee ,  Jae-cheol Lee ,  Sang-yoon Lee ,  Jang-yeon Kwon ,  Kwang-hee Lee ,  Kyoung-seok Son

Inventor： Ji-sim Jung ,  Chang-seung Lee ,  Jae-cheol Lee ,  Sang-yoon Lee ,  Jang-yeon Kwon ,  Kwang-hee Lee ,  Kyoung-seok Son

IPC: H01L29/10 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78606

Abstract: Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a passivation layer on a channel layer, a source, a drain, and a gate, wherein the component of the passivation layer is varied in a height direction. The passivation layer may have a multi-layer structure including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked. The channel layer may include an oxide semiconductor.

Abstract translation: 提供晶体管，晶体管的制造方法和包括该晶体管的电子器件。 晶体管可以包括沟道层上的钝化层，源极，漏极和栅极，其中钝化层的成分在高度方向上变化。 钝化层可以具有依次层叠的包括氧化硅层，氮氧化硅层和氮化硅层的多层结构。 沟道层可以包括氧化物半导体。

公开(公告)号：USD715228S1

公开(公告)日：2014-10-14

申请号：US29418993

申请日：2012-04-24

Applicant: Sang Yoon Lee ,  In Hyeuk Choi ,  Chin Soo Hyon ,  Sang Moon Jeong ,  Hyun Jin Lim

Designer： Sang Yoon Lee ,  In Hyeuk Choi ,  Chin Soo Hyon ,  Sang Moon Jeong ,  Hyun Jin Lim

公开(公告)号：US08715914B2

公开(公告)日：2014-05-06

申请号：US12929151

申请日：2011-01-04

Applicant: Jin Young Kim ,  Soon Taik Hwang ,  Young Hun Byun ,  Euk Che Hwang ,  Sang Yoon Lee

Inventor： Jin Young Kim ,  Soon Taik Hwang ,  Young Hun Byun ,  Euk Che Hwang ,  Sang Yoon Lee

IPC: G03C1/735

CPC classification number: G03F7/0043 ,  G03F7/0042

Abstract: An organometallic composition containing an organometallic compound (I) containing Ag, an organometallic compound (II) containing Au, Pd, or Ru, and an organometallic compound (III) containing Ti, Ta, Cr, Mo, Ru, Ni, Pd, Cu, Au, or Al, wherein the metal components of organometallic compounds (II) and (III), respectively, are present in an amount of 0.01˜10 mol % based on the amount of Ag in the organometallic compound (I), and a method of forming a metal alloy pattern using the same. Silver alloy patterns can be obtained through a simplified manufacturing process, which patterns have enhanced heat resistance, adhesiveness, and chemical stability. The method may be applied to making a reflective film for LCD and metal wiring (gate, source, drain electrode) for flexible displays or flat panel displays, and further to CMP-free damascene processing and PR-free ITO film deposition.

Abstract translation: 含有含Ag的有机金属化合物（I），含有Au，Pd或Ru的有机金属化合物（II）和含有Ti，Ta，Cr，Mo，Ru，Ni，Pd，Cu的有机金属化合物（III）的有机金属组合物 ，Au或Al，其中有机金属化合物（II）和（III）的金属组分分别以有机金属化合物（I）中的Ag的量为0.01〜10摩尔％，和 使用其形成金属合金图案的方法。 可以通过简化的制造工艺获得银合金图案，该图案具有增强的耐热性，粘合性和化学稳定性。 该方法可以应用于制造用于LCD和用于柔性显示器或平板显示器的LCD和金属布线（栅极，源极，漏极）的反射膜，并且还可用于制造无CMP的镶嵌加工和无PR的ITO膜沉积。

公开(公告)号：US08680539B2

公开(公告)日：2014-03-25

申请号：US13304952

申请日：2011-11-28

Applicant: Hong-shik Shim ,  In-seo Kee ,  Sang-yoon Lee

Inventor： Hong-shik Shim ,  In-seo Kee ,  Sang-yoon Lee

IPC: H01L27/32 ,  H01L51/56

CPC classification number: H01L51/5246 ,  H01L25/048 ,  H01L27/3293 ,  H01L51/5262 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A foldable display includes a first plate, a second plate, a first protecting window, a second protecting window, a soft material layer and an intermediate layer which controls brightness. The first plate includes a thin film transistor and an organic light emitting diode (“OLED”), and displays at least one portion of an image to be displayed. The second plate includes a thin film transistor and an OLED, and displays a second portion different from the first portion of the image. The first protecting window is on the first plate. The second protecting window is on the second plate. The soft material layer is between the first and second protecting windows. The intermediate layer is between the soft material layer and a side surface of the first protecting window, and between the soft material layer and the second protecting window.

Abstract translation: 可折叠显示器包括第一板，第二板，第一保护窗，第二保护窗，软材料层和控制亮度的中间层。 第一板包括薄膜晶体管和有机发光二极管（“OLED”），并且显示要显示的图像的至少一部分。 第二板包括薄膜晶体管和OLED，并且显示与图像的第一部分不同的第二部分。 第一个保护窗在第一块板上。 第二个保护窗在第二个板上。 柔软的材料层位于第一和第二保护窗之间。 中间层在软质材料层和第一保护窗的侧表面之间以及软材料层和第二保护窗之间。

公开(公告)号：US08640312B2

公开(公告)日：2014-02-04

申请号：US13469622

申请日：2012-05-11

Applicant: Duk-Hyun Choi ,  Jae-Young Choi ,  Sang-Yoon Lee ,  Sang-Woo Kim

Inventor： Duk-Hyun Choi ,  Jae-Young Choi ,  Sang-Yoon Lee ,  Sang-Woo Kim

IPC: H01L41/22 ,  H01L41/047 ,  H02N2/18

CPC classification number: H02N2/18 ,  H01L41/0478 ,  H01L41/113 ,  H01L41/183 ,  H01L41/31 ,  H01L41/37 ,  H01L51/0032 ,  Y10T29/42 ,  Y10T29/49155 ,  Y10T29/49194

Abstract: A manufacturing method of an apparatus for generating electrical energy according to an embodiment of the present invention comprises disposing a first electrode on a substrate, disposing a nanowire comprising a piezoelectric material on the first electrode, disposing a photoelectric conversion layer which is electrically connected to the nanowire on the first electrode, disposing, a second electrode on the nanowire and the photoelectric conversion layer, connecting the first electrode and the second electrode by a connection part, and disposing a storage part which is electrically connected to the connection part, wherein when an external force is applied to at least one of the first electrode and the second electrode, the nanowire is transformed to generate electrical energy.

Abstract translation: 根据本发明的实施例的用于产生电能的装置的制造方法包括：在基板上设置第一电极，在第一电极上设置包括压电材料的纳米线，设置电连接到第一电极的光电转换层 在所述第一电极上设置纳米线，在所述纳米线上设置第二电极和所述光电转换层，通过连接部连接所述第一电极和所述第二电极，并且设置与所述连接部电连接的存储部， 外力施加到第一电极和第二电极中的至少一个，纳米线被转换以产生电能。

公开(公告)号：US20130221343A1

公开(公告)日：2013-08-29

申请号：US13588462

申请日：2012-08-17

Applicant: Kyoung-seok SON ,  Myung-kwan RYU ,  Tae-sang KIM ,  Hyun-suk KIM ,  Joon-seok PARK ,  Jong-baek SEON ,  Sang-yoon LEE

Inventor： Kyoung-seok SON ,  Myung-kwan RYU ,  Tae-sang KIM ,  Hyun-suk KIM ,  Joon-seok PARK ,  Jong-baek SEON ,  Sang-yoon LEE

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/7869

Abstract: A transistor may include a hole blocking layer between a channel layer including oxynitride and an electrode electrically connected to the channel layer. The hole blocking layer may be disposed in a region between the channel layer and at least one of a source electrode and a drain electrode. The channel layer may include, for example, zinc oxynitride (ZnON). A valence band maximum energy level of the hole blocking layer may be lower than a valence band maximum energy level of the channel layer.

Abstract translation: 晶体管可以包括在包括氮氧化物的沟道层和电连接到沟道层的电极之间的空穴阻挡层。 空穴阻挡层可以设置在沟道层与源电极和漏电极中的至少一个之间的区域中。 沟道层可以包括例如氮氧化锌（ZnON）。 空穴阻挡层的价带最大能级可以低于沟道层的价带最大能级。

公开(公告)号：US20130140551A1

公开(公告)日：2013-06-06

申请号：US13550752

申请日：2012-07-17

Applicant: Joon-seok Park ,  Tae-sang Kim ,  Hyun-suk Kim ,  Myung-kwan Ryu ,  Jong-baek Seon ,  Kyoung-seok Son ,  Sang-yoon Lee ,  Seok-jun Seo

Inventor： Joon-seok Park ,  Tae-sang Kim ,  Hyun-suk Kim ,  Myung-kwan Ryu ,  Jong-baek Seon ,  Kyoung-seok Son ,  Sang-yoon Lee ,  Seok-jun Seo

IPC: H01L29/78 ,  B32B3/26 ,  H01L21/336

CPC classification number: B32B3/26 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869 ,  Y10T428/24479

Abstract: A transistor may include a channel layer formed of an oxide semiconductor. The oxide semiconductor may include GaZnON, and a proportion of Ga content to a total content of Ga and Zn of the channel layer is about 0.5 to about 4.5 at %.

Abstract translation: 晶体管可以包括由氧化物半导体形成的沟道层。 氧化物半导体可以包括GaZnON，并且沟道层的Ga含量与Ga和Zn的总含量的比例为约0.5至约4.5原子％。