公开(公告)号：US06207568B1

公开(公告)日：2001-03-27

申请号：US09200554

申请日：1998-11-27

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/76841 ,  H01L21/2855 ,  H01L21/28568 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.

摘要翻译： 一种形成含铝导体层的方法。 首先提供基板。 然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。 最后，在钛层上形成含有铝的导体层。 通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。 该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。

公开(公告)号：US06191025B1

公开(公告)日：2001-02-20

申请号：US09349847

申请日：1999-07-08

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second dielectric will subsequently act as an etch stop. The third dielectric is a sacrificial layer used to protect the second dielectric. Contact holes are then etched in the layers of first, second, and third dielectric. A first barrier metal and a first conductor metal are then deposited filling the contact hole. The first barrier metal and first conductor metal are then removed down to a level between the original top surface of the layer of third dielectric and the top surface of the second dielectric using a method such as chemical mechanical polishing. The sacrificial third dielectric protects the layer of second dielectric during the chemical mechanical polishing. A layer of fourth dielectric is then deposited. Trenches are then etched in the fourth dielectric using the second dielectric, which has been maintained intact by the sacrificial third dielectric, as an etch stop. The trenches are then filled with a second barrier metal and second conductor metal. Excess second barrier metal and second conductor metal are then removed using chemical mechanical polishing to complete the damascene structure.

摘要翻译： 一种制造铜导体镶嵌结构的方法。 在其上形成有器件的硅衬底上形成第一，第二和第三电介质层。 第二电介质将随后作为蚀刻停止。 第三电介质是用于保护第二电介质的牺牲层。 然后在第一，第二和第三电介质的层中蚀刻接触孔。 然后沉积第一阻挡金属和第一导体金属，填充接触孔。 然后使用诸如化学机械抛光的方法将第一阻挡金属和第一导体金属去除到第三电介质层的原始顶表面和第二电介质的顶表面之间的水平。 牺牲的第三绝缘体在化学机械抛光期间保护第二电介质层。 然后沉积第四电介质层。 然后使用已被牺牲的第三电介质保持的第二电介质作为蚀刻停止层，在第四电介质中蚀刻沟槽。 然后用第二阻挡金属和第二导体金属填充沟槽。 然后使用化学机械抛光去除过量的第二阻挡金属和第二导体金属，以完成镶嵌结构。

公开(公告)号：US6165052A

公开(公告)日：2000-12-26

申请号：US192518

申请日：1998-11-16

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： B24B37/04 ,  B24B49/16 ,  H01L21/306 ,  B24B1/00

CPC分类号： B24B37/013 ,  B24B37/04 ,  B24B37/042 ,  B24B49/16 ,  H01L21/30625

摘要： A method to planarize the surface of a semiconductor substrate having shallow trench isolation (STI) reduces erosion of a silicon nitride planarization stop layer, reduces dishing of large areas of the shallow trench isolation, and prevents under polishing of the surface of the semiconductor substrate that will leave portions of the silicon dioxide that fills the shallow trenches covering the silicon nitride planarization stop exposed, is described. The method to planarize the surface of a semiconductor substrate having shallow trenches begins by chemical/mechanical planarization polishing at a first product of platen pressure and platen speed to planarize the semiconductor substrate. Polishing at a first product of platen pressure and platen speed will cause a high rate of material removal with low selectivity to increase production throughput. The silicon nitride stop layer will be examined to determine an end point exposure of the silicon nitride stop layer. When the end point exposure of the silicon nitride stop layer is reached, chemical/mechanical planarization polishing at a low product of platen pressure and platen speed is started to planarize the semiconductor substrate of slow over polish to control thickness of a trench oxide of the shallow trench isolation to reduce dishing and minimize erosion. The method further has the step of buffing the surface of the semiconductor substrate to remove any residue from the chemical/mechanical planarization polishing and to remove any microscratches from the surface of the semiconductor substrate.

摘要翻译： 平坦化具有浅沟槽隔离（STI）的半导体衬底的表面的方法减少了氮化硅平坦化停止层的侵蚀，减少了大面积浅沟槽隔离的凹陷，并且防止在半导体衬底的表面的抛光 将描述填充覆盖氮化硅平坦化止挡露出的浅沟槽的二氧化硅部分。 平面化具有浅沟槽的半导体衬底的表面的方法开始于在压板压力和压板速度的第一乘积上的化学/机械平面化抛光，以使半导体衬底平坦化。 在压板压力和压板速度的第一个产品上进行抛光将导致高选择性的材料去除率，从而提高生产量。 将检查氮化硅阻挡层以确定氮化硅阻挡层的端点暴露。 当达到氮化硅终止层的终点曝光时，开始以压板压力和压板速度的低乘积进行化学/机械平面化抛光，以平缓化缓慢过抛光的半导体衬底，以控制浅层的沟槽氧化物的厚度 沟槽隔离以减少凹陷和最小化侵蚀。 该方法还具有抛光半导体衬底的表面以从化学/机械平面化抛光中除去任何残余物并从半导体衬底的表面去除任何微细凹凸的步骤。

公开(公告)号：US6130157A

公开(公告)日：2000-10-10

申请号：US356005

申请日：1999-07-16

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76879

摘要： A method to form copper interconnects with an improved encapsulation layer is achieved. A substrate layer is provided. Conductive traces are provided overlying the substrate layer. A first intermetal dielectric layer is deposited overlying the conductive traces. The first intermetal dielectric layer is etched through to the underlying conductive traces where the first intermetal dielectric layer is not protected by a photoresist mask to form interconnect trenches. A barrier layer is deposited overlying the first intermetal dielectric layer and exposed the conductive traces. A copper layer is deposited overlying the barrier layer and filling the interconnect trenches. The copper layer and the barrier layer are polished down to the top surface of the first intermetal dielectric layer to define copper interconnects. An encapsulation layer is formed overlying the copper interconnects wherein the encapsulation layer is not formed overlying the first intermetal interconnect layer and wherein the encapsulation layer is at least partially comprised of tungsten nitride. A second intermetal dielectric layer is deposited and the fabrication of the integrated circuit device is completed.

摘要翻译： 实现了与改进的封装层形成铜互连的方法。 提供基底层。 覆盖衬底层的导电迹线被提供。 第一金属间电介质层沉积在导电迹线上。 第一金属间电介质层被蚀刻到下面的导电迹线，其中第一金属间电介质层不被光致抗蚀剂掩模保护以形成互连沟槽。 沉积覆盖在第一金属间电介质层上并且暴露导电迹线的阻挡层。 沉积铜层沉积在阻挡层上并填充互连沟槽。 铜层和阻挡层被抛光到第一金属间电介质层的顶表面以限定铜互连。 形成覆盖铜互连的封装层，其中封装层没有形成在第一金属间互连层上，其中封装层至少部分地由氮化钨组成。 沉积第二金属间电介质层并完成集成电路器件的制造。

公开(公告)号：US6114253A

公开(公告)日：2000-09-05

申请号：US268542

申请日：1999-03-15

申请人： Syun-Ming Jang ,  Ming-Hsin Huang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ming-Hsin Huang ,  Chen-Hua Yu

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31055

摘要： A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.

摘要翻译： 描述了用于去除用于蚀刻低k有机聚合物介电层中的通孔的残余氧化硅硬掩模的工艺。 当用于在高密度等离子体蚀刻机中在氧气/惰性气体等离子体中蚀刻有机聚合物层时，通过沿着图案边缘开发角度方面或刻面，硬掩模劣化。 此外，在有机聚合物蚀刻期间硬掩模的劣化导致表面平面度的显着降低，这会在将硬掩模留在原位时在其上形成第二金属层时导致通孔到通孔短路。 在通过等离子体蚀刻的通孔蚀刻之后立即选择性地去除残余硬掩模，该等离子体蚀刻恢复表面平面度并且经由边缘面移除。 等离子体蚀刻具有高的氧化物对有机聚合物的选择性，使得表面不规则性不会转移到聚合物表面，并且通孔底部的暴露的金属表面也是无损的。

公开(公告)号：US6010962A

公开(公告)日：2000-01-04

申请号：US249262

申请日：1999-02-12

申请人： Chung-Shi Liu ,  Chung-Long Chang ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chung-Long Chang ,  Chen-Hua Yu

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76879 ,  H01L21/32115

摘要： A method is disclosed for forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical-mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate including a composite groove/hole structure already formed in an insulating layer and then growing a copper seed layer over the barrier layer. A layer of photoresist is next deposited over the substrate filling the composite structure. The photoresist layer, seed layer and the barrier layer are then removed by chemical-mechanical polishing, leaving the seed layer and the barrier layer on the inside walls of the composite structure, however. Then the photoresist is removed from the composite structure, and replaced, in its place, with electroless plated copper, which forms a dome-like protrusion extending from the composite structure. When the substrate is subjected to chemical-mechanical polishing in order to remove the excess copper, the dome-like structure prevents the dishing of the copper metal. In a second embodiment, the seed layer and the barrier layer are chemical-mechanical polished without first depositing a photoresist layer. Copper metal is next selectively formed by electroless plating having a dome-like protrusion, which in turn is removed by chemical-mechanical polishing without the detrimental formation of dishing in the copper metal.

摘要翻译： 公开了一种用于在绝缘层中形成镶嵌铜互连的方法，而不会在多余的铜的化学机械抛光之后发生通常预期的凹陷。 这通过在包括已经形成在绝缘层中的复合凹槽/孔结构的衬底上形成共形覆盖层阻挡层，然后在阻挡层上生长铜籽晶层来实现。 接着在填充复合结构的基板上沉积一层光致抗蚀剂。 然后通过化学机械抛光除去光致抗蚀剂层，种子层和阻挡层，然而将种子层和阻挡层留在复合结构的内壁上。 然后将光致抗蚀剂从复合结构中去除，并在其位置上用化学镀铜替代，其形成从复合结构延伸的圆顶状突起。 当基板进行化学机械抛光以去除多余的铜时，圆顶状结构防止铜金属的凹陷。 在第二实施例中，晶种层和阻挡层在没有首先沉积光致抗蚀剂层的情况下进行化学机械抛光。 接下来通过具有圆顶状突起的化学镀选择性地形成铜金属，其通过化学机械抛光而被除去，而不会有害地形成铜金属中的凹陷。

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US5922516A

公开(公告)日：1999-07-13

申请号：US868677

申请日：1997-06-04

申请人： Chen-Hua Yu ,  Chia-Shiung Tsai

发明人： Chen-Hua Yu ,  Chia-Shiung Tsai

IPC分类号： G03F7/095 ,  G03F7/26 ,  G03F7/38

CPC分类号： G03F7/265 ,  G03F7/095

摘要： A new method of improving critical dimension control by using a silylation process with a cross-linked photoresist underlayer is described. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first photoresist layer. The first photoresist layer is baked. The first photoresist layer is coated with a second photoresist layer. A portion of the second photoresist layer not covered by a mask is exposed to actinic light. Thereafter, the exposed portion of the second photoresist layer is baked, then silylated. The silylated portion of the second photoresist layer and the underlying first photoresist layer forms the photomask. The remaining second and first photoresist layers not covered by the photomask are etched away. The layer to be etched is etched away where it is not covered by the photomask and the photomask is removed to complete the photoetching having uniform critical dimension in the fabrication of an integrated circuit.

摘要翻译： 描述了通过使用具有交联光致抗蚀剂底层的甲硅烷化方法来改进关键尺寸控制的新方法。 要蚀刻的层被提供在半导体衬底上，其中该层的表面具有不均匀的形貌。 待蚀刻的层被涂覆有第一光致抗蚀剂层。 第一光致抗蚀剂层被烘烤。 第一光致抗蚀剂层被涂覆有第二光致抗蚀剂层。 未被掩模覆盖的第二光致抗蚀剂层的一部分暴露于光化光。 此后，将第二光致抗蚀剂层的暴露部分烘焙，然后进行甲硅烷基化。 第二光致抗蚀剂层和下面的第一光致抗蚀剂层的甲硅烷基化部分形成光掩模。 未被光掩模覆盖的剩余的第二和第一光致抗蚀剂层被蚀刻掉。 要蚀刻的层被蚀刻掉，其中它不被光掩模覆盖，并且除去光掩模以完成在制造集成电路中具有均匀临界尺寸的光刻。

公开(公告)号：US5871886A

公开(公告)日：1999-02-16

申请号：US764288

申请日：1996-12-12

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： G03F7/09 ,  H01L21/027 ,  G03F7/00

CPC分类号： H01L21/0276 ,  G03F7/091

摘要： A method of patterning a layer of reflective material, such as a layer of conductor metal, using a layer of antireflection coating material sandwiched between two layers of photoresist. A first layer of photoresist is formed on an integrated circuit wafer and provides a planar surface for subsequent layers of material. A layer of antireflection coating material is formed on the layer of first photoresist and a layer of second photoresist is formed on the layer of antireflection coating material. The layer of second photoresist is selectively exposed and developed. The layer of antireflection coating material is patterned using dry etching and the patterned layer of second photoresist as a mask. The layer of first photoresist is then patterned using dry etching and the patterned layer of antireflection coating material as a mask. The layer of reflecting material is then patterned using dry etching and the patterned layer of first photoresist as a mask. The patterned layer of first photoresist is then removed.

摘要翻译： 使用夹在两层光致抗蚀剂之间的抗反射涂层层来图案化反射材料层（例如导体金属层）的方法。 在集成电路晶片上形成第一层光致抗蚀剂，并为随后的材料层提供平面。 在第一光致抗蚀剂层上形成防反射涂层，在抗反射涂层层上形成第二光致抗蚀剂层。 选择性地曝光和显影第二光致抗蚀剂层。 使用干蚀刻和第二光致抗蚀剂的图案化层作为掩模来图案化抗反射涂层材料层。 然后使用干蚀刻和防反射涂层材料的图案化层作为掩模来将第一光致抗蚀剂层图案化。 然后使用干蚀刻和第一光致抗蚀剂的图案化层作为掩模来图案化反射材料层。 然后去除第一光致抗蚀剂的图案化层。

公开(公告)号：US5747380A

公开(公告)日：1998-05-05

申请号：US606833

申请日：1996-02-26

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： H01L21/66 ,  H01L21/768 ,  H01L21/44

CPC分类号： B24B37/013 ,  H01L21/768 ,  H01L22/26 ,  Y10S438/926

摘要： A method for improving the end-point detection for contact and via etching is disclosed. The disclosure describes the deliberate addition of dummy patterns in the form of contact and via holes to the regular functional holes in order to increase the amount of etchable surface area. It is shown that, one can then take advantage of the marked change in the composition of the etchant gas species that occurs as soon as what was once a large exposed area has now been consumed through the etching process. This then gives a strong and robust signal for the end of the etching process. This in turn results in better controlled and more reliable product. It is also indicated that with the full uniform pattern of the via layers now possible, the chemical/mechanical polishing process becomes much less pattern sensitive.

摘要翻译： 公开了一种用于改善接触和通孔蚀刻的端点检测的方法。 本公开描述了将接触孔和通孔形式的虚拟图案有意添加到常规功能孔，以增加可蚀刻表面积的量。 可以看出，一旦现在通过蚀刻工艺消耗了大的暴露区域，就可以利用所发生的蚀刻剂气体种类的组成的明显变化。 这就为腐蚀过程的结束提供了一个强大而鲁棒的信号。 这反过来导致更好的控制和更可靠的产品。 还指出，现在可能通孔层的完全均匀图案，化学/机械抛光工艺变得更加模式敏感。