公开(公告)号：US10580701B1

公开(公告)日：2020-03-03

申请号：US16168441

申请日：2018-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Scott Beasor ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a gate structure in a gate cavity laterally defined by a sidewall spacer and recessing the sidewall spacer so as to form a recessed sidewall spacer with a recessed upper surface is disclosed. In this example, the method also includes performing at least one etching process to form a tapered upper surface on the exposed portion of the gate structure above the recessed upper surface of the spacer and forming a gate cap above the tapered upper surface of the gate structure and above the recessed upper surface of the recessed sidewall spacer.

公开(公告)号：US10580685B2

公开(公告)日：2020-03-03

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Hong Yu ,  Laertis Economikos

IPC: H01L23/522 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/764

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

公开(公告)号：US20200044034A1

公开(公告)日：2020-02-06

申请号：US16054033

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Kevin J. Ryan ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/06

Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

公开(公告)号：US20200043779A1

公开(公告)日：2020-02-06

申请号：US16052085

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC: H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/28

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US10553707B1

公开(公告)日：2020-02-04

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US20200020770A1

公开(公告)日：2020-01-16

申请号：US16033812

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu ,  George R. Mulfinger

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: Structures for field-effect transistors and methods for forming field-effect transistors. A sidewall spacer is arranged adjacent to a sidewall of a gate structure. The sidewall spacer includes a first section and a second section arranged over the first section. The first section of the sidewall spacer is composed of a first dielectric material, and the second section of the sidewall spacer is composed of a second dielectric material different from the first dielectric material. A source/drain region includes a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer. The second section of the source/drain region is spaced by a gap from the second section of the sidewall spacer.

公开(公告)号：US20200020687A1

公开(公告)日：2020-01-16

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

公开(公告)号：US20200020631A1

公开(公告)日：2020-01-16

申请号：US16578844

申请日：2019-09-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

公开(公告)号：US10522644B1

公开(公告)日：2019-12-31

申请号：US16014076

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Scott Beasor

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.

公开(公告)号：US20190393212A1

公开(公告)日：2019-12-26

申请号：US16016058

申请日：2018-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/51 ,  H01L49/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/66

Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.