公开(公告)号：US11205622B2

公开(公告)日：2021-12-21

申请号：US16423561

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/552 ,  H01L23/522

Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.

公开(公告)号：US11177226B2

公开(公告)日：2021-11-16

申请号：US16450266

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H01L23/60 ,  H01L23/48 ,  H01L25/07 ,  H01L25/11 ,  H01L25/065

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

公开(公告)号：US11164827B2

公开(公告)日：2021-11-02

申请号：US16473962

申请日：2017-12-19

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

公开(公告)号：US20210320051A1

公开(公告)日：2021-10-14

申请号：US17155757

申请日：2021-01-22

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20210183755A1

公开(公告)日：2021-06-17

申请号：US17023042

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/498 ,  H01L23/552 ,  H01L21/48

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.

公开(公告)号：US20210167023A1

公开(公告)日：2021-06-03

申请号：US17125593

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/528 ,  H01L49/02 ,  H01L23/50 ,  H01L23/13

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

公开(公告)号：US10957649B2

公开(公告)日：2021-03-23

申请号：US16329080

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L23/48 ,  H01L23/538 ,  H01L29/06 ,  H01L23/00 ,  H01L25/065 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498

Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.

公开(公告)号：US10910325B2

公开(公告)日：2021-02-02

申请号：US15974393

申请日：2018-05-08

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/528 ,  H01L49/02 ,  H01L23/50 ,  H01L23/13 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

公开(公告)号：US10856407B2

公开(公告)日：2020-12-01

申请号：US16021618

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Stephen Harvey Hall ,  Yun Rou Lim

IPC: H01P3/08 ,  H05K1/02 ,  H01L23/64 ,  H01L23/498 ,  H01P3/10 ,  H01P9/00 ,  H03H7/38 ,  H01L23/66

Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.

公开(公告)号：US10748854B2

公开(公告)日：2020-08-18

申请号：US16079534

申请日：2016-03-16

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Hungying Louis Lo

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/60 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/29 ,  H01L25/10 ,  H01L25/18

Abstract: Disclosed herein are stairstep interposers with integrated conductive shields, and related assemblies and techniques. In some embodiments, an interposer may include: an insulating material having a stairstep structure with a first step surface, a second step surface, and a bottom surface to face a package substrate, wherein a first thickness of the insulating material between the first step surface and the bottom surface is greater than a second thickness of the insulating material between the second step surface and the bottom surface; a conductive signal pathway extending from the first step surface to the bottom surface; and a conductive shield disposed within the insulating material to shield the conductive signal pathway.