公开(公告)号：US6162738A

公开(公告)日：2000-12-19

申请号：US144857

申请日：1998-09-01

Applicant: Gary Chen ,  Li Li

Inventor： Gary Chen ,  Li Li

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/302

CPC classification number: H01L21/02071 ,  H01L21/32134 ,  H01L21/32138

Abstract: A cleaning method includes providing a stack including at least a layer of Ta.sub.2 O.sub.5 and a layer of conductive material. The stack includes a conductive etch residue on at least portions thereof. A dilute aqueous composition is provided including hydrochloric acid (HCl), hydrogen peroxide (H.sub.2 O.sub.2), and deionized water (H.sub.2 O). The stack is exposed to the dilute aqueous composition to remove the conductive etch residue. The dilute aqueous composition may include a ratio of H.sub.2 O:H.sub.2 O.sub.2 :HCl in a range of about 100:1:0.5 to about 100:10:5. A cleaning composition for use in the method includes a dilute aqueous composition including hydrochloric acid (HCl), hydrogen peroxide (H.sub.2 O.sub.2), and deionized water (H.sub.2 O).

Abstract translation: 清洁方法包括提供包括至少一层Ta 2 O 5层和导电材料层的堆叠。 该堆叠在其至少部分上包括导电蚀刻残留物。 提供了一种稀释的水性组合物，包括盐酸（HCl），过氧化氢（H 2 O 2）和去离子水（H 2 O）。 将该堆叠暴露于稀释的含水组合物以除去导电蚀刻残留物。 该稀水性组合物可以包括在约100:1:0.5至约100:10:5的范围内的H 2 O:H 2 O 2 :HCl的比例。 用于该方法的清洁组合物包括含有盐酸（HCl），过氧化氢（H 2 O 2）和去离子水（H 2 O）的稀释水性组合物。

公开(公告)号：US6117791A

公开(公告)日：2000-09-12

申请号：US102152

申请日：1998-06-22

Applicant: Kei-Yu Ko ,  Li Li ,  Guy T. Blalock

Inventor： Kei-Yu Ko ,  Li Li ,  Guy T. Blalock

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/302

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: An etchant including C.sub.2 H.sub.x F.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C.sub.2 H.sub.x F.sub.y -containing etchant. C.sub.2 H.sub.x F.sub.y may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.

公开(公告)号：US6083849A

公开(公告)日：2000-07-04

申请号：US18228

申请日：1998-02-03

Applicant: Er-Xuan Ping ,  Li Li

Inventor： Er-Xuan Ping ,  Li Li

IPC: C09K13/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/302

CPC classification number: H01L21/02049 ,  C09K13/06 ,  H01L21/02063 ,  H01L21/02068 ,  H01L28/84

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40.degree. C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40.degree. C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40.degree. C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract translation: 一方面，本发明包括一种半导体处理方法，其包括将表面与包含至少一种含氟物质的液体溶液和至少约40℃的温度接触。另一方面，本发明包括一种钝化方法 含硅层包括使该层与包含氟化氢的液体溶液接触并且至少约40℃的温度。在另一方面，本发明包括形成半球形晶粒多晶硅的方法，包括：a）形成包括基本上 非晶硅; b）使包含基本上非晶硅的层与包含含氟物质的液体溶液和至少约40℃的温度接触; c）将包含基本上非晶硅的层接种; 以及d）退火所述接种层以将所述接种层的至少一部分转化为半球形晶粒多晶硅。

公开(公告)号：US6049101A

公开(公告)日：2000-04-11

申请号：US36702

申请日：1998-03-06

Applicant: Thomas M. Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

Inventor： Thomas M. Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

Abstract: Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

公开(公告)号：US6027967A

公开(公告)日：2000-02-22

申请号：US887744

申请日：1997-07-03

Applicant: Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

Inventor： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82

Abstract: A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to create a structure with spaced apart doped polysilicon layers. A dielectric layer and an electrically conductive cell plate are formed over the alternating layers of the doped polysilicon and the undoped polysilicon. The semiconductor substrate is heated to diffuse dopant in the doped polysilicon into the undoped polysilicon. The resultant novel capacitor has a fin-like structure extending therefrom which increase the surface area thereof.

Abstract translation: 一种制造电容器的方法，包括提供在半导体衬底上的一对栅极堆叠之间延伸的空间，该空间暴露半导体衬底上的电荷传导区域。 在一对栅极叠层上形成BPSG层。 在沉积多晶硅的单个沉积循环期间，在BPSG层上形成包括掺杂多晶硅和未掺杂多晶硅交替层的硬掩模层。 选择性地去除硬掩模层和BPSG层的部分以形成在栅叠层之上延伸并且在它们之间具有沟槽的拓扑结构。 执行间隔物蚀刻和接触蚀刻以暴露电荷导电区域。 在每个形貌结构的侧面上形成掺杂的多晶硅间隔物。 掺杂多晶硅和未掺杂多晶硅的第二组交替层形成在拓扑结构之上和沟槽内。 选择性地去除了硬掩模层和掺杂多晶硅和未掺杂多晶硅的交替层的第二组的部分。 执行对掺杂多晶硅选择性的蚀刻以选择性地去除未掺杂的多晶硅以产生具有间隔开的掺杂多晶硅层的结构。 在掺杂多晶硅和未掺杂多晶硅的交替层上形成介电层和导电单元板。 加热半导体衬底以将掺杂多晶硅中的掺杂剂扩散到未掺杂的多晶硅中。 所得到的新型电容器具有从其延伸的鳍状结构，其增加其表面积。

公开(公告)号：US5786250A

公开(公告)日：1998-07-28

申请号：US818597

申请日：1997-03-14

Applicant: Zhiqiang Wu ,  Li Li ,  Kunal Parekh

Inventor： Zhiqiang Wu ,  Li Li ,  Kunal Parekh

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1085 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

Abstract: A method of the present invention forms a vertically oriented structure connected with a source/drain region through an open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad. A dry etching process is used to remove a segment of the conductive layer formed over the volume of insulating material upon the landing pad, after which the volume of insulating material upon the landing pad is removed. Remaining is a storage node made upon of a continuous layer of conductive material that lines the recess and the open space. A dielectric layer and a cell plate are in one embodiment formed over the continuous layer of conducting material so as to extend down into the open space, thus completing a container capacitor.

Abstract translation: 本发明的方法形成了通过开放空间与源极/漏极区域连接的垂直取向结构。 在其中形成电容器存储节点的方法的一个实施例中，开放空间位于MOS DRAM存储器电路中的两个字线栅极叠层之间。 薄的着陆板由导电材料形成，该导电材料在延伸到源极/漏极区域以及栅极堆叠顶部的开放空间中。 绝缘层形成在栅极叠层和着陆焊盘上。 通过绝缘层向下蚀刻凹陷以暴露着陆垫的环形部分。 绝缘材料的体积留在开放空间中的着陆垫上。 导电层沉积在与着陆焊盘暴露的环形部分接触的凹部中。 使用干蚀刻工艺去除在着陆焊盘上形成在绝缘材料体积上的导电层的段，之后移除着陆焊盘上的绝缘材料的体积。 剩余的是由连续的导电材料层制成的存储节点，其导引凹槽和开放空间。 在一个实施例中，在导电材料的连续层上形成电介质层和电池板，以便向下延伸到开放空间中，从而完成容器电容器。

公开(公告)号：US5619059A

公开(公告)日：1997-04-08

申请号：US314003

申请日：1994-09-28

Applicant: Li Li ,  Jerzy A. Dobrowolski ,  Peter D. Grant ,  Brian T. Sullivan

Inventor： Li Li ,  Jerzy A. Dobrowolski ,  Peter D. Grant ,  Brian T. Sullivan

IPC: G02B26/08 ,  H01L27/14 ,  H01L31/00

CPC classification number: G02B26/0841

Abstract: A semiconductor device comprises a plurality of colored deformable mirrors controllable by electrical circuitry. Groups of mirrors, responsive to the electronic signals, are selectably operable to reflect incident light. The deformable mirrors are coated with an optical thin film interference color coating having at least a layer that is substantially transparent to the visible light. As well the optical thin film interference color coating includes at least one further layer that is partially absorbing with respect to the visible light. The spectral reflectance and absorptance of the deformable mirror is modified in order to obtain a desired reflected color by the process of optical interference enhanced absorption in the optical thin film interference color coating. The optical thin film interference color coating has predetermined layer thicknesses and materials; the substantially transparent layer substantially determines the desired reflected color.

Abstract translation: 半导体器件包括可由电路控制的多个有色可变形反射镜。 响应于电子信号的反射镜组可选择地可操作以反射入射光。 可变形反射镜涂覆有至少具有对可见光基本上透明的层的光学薄膜干涉色涂层。 此外，光学薄膜干涉色涂层还包括相对于可见光部分吸收的至少一个另外的层。 修改可变形反射镜的光谱反射率和吸收率，以便通过在光学薄膜干涉色涂层中的光学干涉增强吸收的过程获得期望的反射颜色。 光学薄膜干涉色涂层具有预定的层厚度和材料; 基本上透明的层基本上确定所需的反射颜色。

公开(公告)号：US5526906A

公开(公告)日：1996-06-18

申请号：US343795

申请日：1994-11-22

Applicant: J. Kim Vandiver ,  Li Li

Inventor： J. Kim Vandiver ,  Li Li

IPC: B63B21/66 ,  B63B39/00 ,  E01D19/16 ,  F16F7/14 ,  F16F15/02

CPC classification number: B63B21/66 ,  B63B39/005 ,  E01D19/16 ,  F16F15/02 ,  F16F7/14

Abstract: The invention is an apparatus for connecting a slender structure to a reference body. The apparatus comprises a link, that is connected to one end of the slender structure. The link is connected with a hinge at a second point of the link to the reference body with at least one degree of rotational freedom. A damper for damping motion of the link through at least one of the link's degrees of rotational freedom is connected between the link at a third point and the reference body. The device suppresses vibration waves travelling in the slender structure. A spring for resisting motion through the degree of rotational freedom may also be beneficially provided. The link, spring and damper may all act through one or two degrees of rotational freedom. The hinge can be either a pivot or a flex joint. The invention includes a method of selecting the parameters of the link, damper and spring assembly to optimize the suppression of vibration.

Abstract translation: 本发明是用于将细长结构连接到参考体的装置。 该装置包括连接到细长结构的一端的连杆。 该连杆在至少一个旋转自由度的连接到参考体的第二点处与铰链连接。 用于通过链节的旋转自由度中的至少一个阻尼链节的运动的阻尼器连接在第三点处的连杆和参考体之间。 该装置抑制在细长结构中行进的振动波。 还可以有益地提供用于抵抗旋转自由度的运动的弹簧。 连杆，弹簧和阻尼器都可以通过一个或两个旋转自由度。 铰链可以是枢轴或挠性接头。 本发明包括选择连杆，减震器和弹簧组件的参数以优化振动抑制的方法。

公开(公告)号：US20250025270A1

公开(公告)日：2025-01-23

申请号：US18684276

申请日：2022-09-22

Applicant: Danyang L. YUE ,  Li LI

Inventor： Danyang L. Yue ,  Xin Shu Yue ,  Li Li ,  Yingge Yue

IPC: A61C15/04 ,  A61K8/21 ,  A61Q11/00

Abstract: A dental floss is provided. The dental floss contains gum care actives for gum disease prevention and treatment without staining or bitter taste.

公开(公告)号：US12150670B1

公开(公告)日：2024-11-26

申请号：US18767070

申请日：2024-07-09

Applicant: Li Li

Inventor： Li Li ,  Guowen Zhao

IPC: A61B17/3209 ,  A61B17/3211

Abstract: Disclosed is a pet intraurethral incision knife, including a knife rod, a blade, and a guide wire, a blade slot is formed on one side of the knife rod, the hollow cavity is formed inside the knife rod in the length direction, the hollow cavity is communicated with the bottom of the blade slot, the blade can be rotationally retracted inside the blade slot, one end of the guide wire is abutted against an edge of one end of the blade, and the other end thereof passes through the hollow cavity and forms an operating end at one end of the knife rod, such that the operating end drives one end of the guide wire to push the blade to rotate and to be exposed from the opening of the blade slot, the blade can be hidden and stored inside the blade slot before being inserted into a pet urethra.