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    Memory Arrays and Methods of Forming Memory Arrays
    164.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权

    公开(公告)号：US20170148852A1

    公开(公告)日：2017-05-25

    申请号：US15421855

    申请日：2017-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

    Memory cells, integrated devices, and methods of forming memory cells
    165.
    发明授权
    Memory cells, integrated devices, and methods of forming memory cells 有权
    存储单元，集成器件和形成存储单元的方法

    公开(公告)号：US09570677B2

    公开(公告)日：2017-02-14

    申请号：US15049100

    申请日：2016-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Ugo Russo ,  Agostino Pirovano ,  Simone Lavizzari

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

    Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

    Abstract translation: 一些实施例包括集成设备，诸如存储器单元。 这些装置可以包括硫族化物材料，在硫族化物材料上的导电材料，以及在导电材料和硫族化物材料之间的散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。 一些实施例包括形成存储器单元的方法。 可以在加热器材料上形成硫族化物材料。 可以在硫族化物材料上形成导电材料。 可以在导电材料和硫族化物材料之间形成散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。

    Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays
    166.
    发明申请
    Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays 有权
    内存单元，内存阵列和形成内存单元和阵列的方法

    公开(公告)号：US20170018708A1

    公开(公告)日：2017-01-19

    申请号：US15279158

    申请日：2016-09-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

    Memory Arrays and Methods of Forming Memory Arrays
    168.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权

    公开(公告)号：US20160190443A1

    公开(公告)日：2016-06-30

    申请号：US15064002

    申请日：2016-03-08

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

    Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

    Memory constructions
    170.
    发明授权
    Memory constructions 有权
    内存结构

    公开(公告)号：US08987698B2

    公开(公告)日：2015-03-24

    申请号：US14503081

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。

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