公开(公告)号：US20140189466A1

公开(公告)日：2014-07-03

申请号：US14200665

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/16

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

Abstract translation: 提供了用于检测和校正存储器系统中的地址错误的系统和方法。 在存储器系统中，存储器件基于通过地址总线发送的地址生成错误检测码，并将错误检测码发送到存储器控制器。 存储器控制器响应于错误检测码向存储器件发送错误指示。 错误指示使存储器件移除接收的地址并防止存储器操作

公开(公告)号：US12136452B2

公开(公告)日：2024-11-05

申请号：US18209976

申请日：2023-06-14

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G06F1/08 ,  G06F3/06 ,  G06F5/06 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/409 ,  G11C29/02 ,  G11C11/4096

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20240020258A1

公开(公告)日：2024-01-18

申请号：US18355660

申请日：2023-07-20

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1694

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20230326513A1

公开(公告)日：2023-10-12

申请号：US18103386

申请日：2023-01-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C11/4096 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  Y02D30/50 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/4087 ,  Y02D10/00 ,  G11C11/4074

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US11782863B2

公开(公告)日：2023-10-10

申请号：US17826056

申请日：2022-05-26

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/00

Abstract: A memory module includes memory devices and a configurable command buffer that selects between alternative command ports for controlling different groupings of the memory devices. Memory systems with memory modules incorporating such a command buffer and memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths.

公开(公告)号：US11587605B2

公开(公告)日：2023-02-21

申请号：US17341048

申请日：2021-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20220398206A1

公开(公告)日：2022-12-15

申请号：US17809688

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20220374381A1

公开(公告)日：2022-11-24

申请号：US17826056

申请日：2022-05-26

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16

Abstract: A memory module includes memory devices and a configurable command buffer that selects between alternative command ports for controlling different groupings of the memory devices. Memory systems with memory modules incorporating such a command buffer and memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths.

公开(公告)号：US11409682B2

公开(公告)日：2022-08-09

申请号：US16950861

申请日：2020-11-17

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20210225417A1

公开(公告)日：2021-07-22

申请号：US17222388

申请日：2021-04-05

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22 ,  G11C5/06 ,  G11C29/02 ,  G11C11/4063

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.