公开(公告)号：US20080040054A1

公开(公告)日：2008-02-14

申请号：US11768922

申请日：2007-06-27

Applicant: SHOU-KUO HSU ,  CHIA-NAN PAI ,  CHENG-SHIEN LI

Inventor： SHOU-KUO HSU ,  CHIA-NAN PAI ,  CHENG-SHIEN LI

IPC: G01R15/00

CPC classification number: G06F17/5036 ,  G01R31/025 ,  G01R31/041

Abstract: A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.

Abstract translation: 公开了一种用于分析信号路径的分支长度的系统。 该系统包括：用于命名PCB的所有信号路径的信号路径命名模块; 信号路径组选择模块，用于从数据库中选择要分析的一组信号路径; 信号路径选择模块，用于从信号路径组中选择要分析的信号路径; 用于分析所选择的信号路径的分支搜索模块，搜索与所选择的信号路径连接的无源电路组件和外部电路用于所选择的信号路径的相应分支; 分支长度计算模块，用于计算每个分支的长度; 以及分支长度比较模块，用于将每个计算的分支长度与相应的预定义的最大分支长度进行比较，以确定所计算的分支长度是否大于预定的最大分支长度。 还公开了相关方法。

公开(公告)号：US20070291459A1

公开(公告)日：2007-12-20

申请号：US11558472

申请日：2006-11-10

Applicant: SHOU-KUO HSU ,  YU-CHANG PAI ,  CHUN-JEN CHEN

Inventor： SHOU-KUO HSU ,  YU-CHANG PAI ,  CHUN-JEN CHEN

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0234 ,  H05K1/0225 ,  H05K1/0231 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10022

Abstract: An exemplary circuit board includes a power plane with a first metal plate, a ground plane with a second metal plate, a channel etched in one of the metal plates to define an isolated area therein, and a coupling circuit. A gap is formed between the isolated area and other area of the one of the metal plates. The coupling circuit is electronically connected between the first and the second metal plates in the isolated area for reducing a resonance frequency caused by the channel. The circuit board can reduce electromagnetic interference generated therein.

Abstract translation: 示例性电路板包括具有第一金属板的电源平面，具有第二金属板的接地平面，在其中一个金属板中蚀刻以在其中限定隔离区域的沟道以及耦合电路。 在隔离区域和金属板之一的其它区域之间形成间隙。 耦合电路电连接在隔离区域中的第一和第二金属板之间，以减少由通道引起的谐振频率。 电路板可以减少其中产生的电磁干扰。

公开(公告)号：US20070139058A1

公开(公告)日：2007-06-21

申请号：US11552975

申请日：2006-10-26

Applicant: SHOU-KUO HSU ,  CHENG-SHIEN LI

Inventor： SHOU-KUO HSU ,  CHENG-SHIEN LI

IPC: G01R27/28

CPC classification number: G01R31/31725 ,  G01R31/318357 ,  G06F17/5036

Abstract: A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device (9); simulating the differential signal paths based on the design file; dividing simulated differential signal paths into a plurality of segments by impedance division positions that show impedance discontinuity; predefining an acceptable length difference limit for each divided segment, and calculating an real length difference for each divided segment; comparing the real length difference with the acceptable length difference limit correspondingly to generate a plurality of analyzed results corresponding to the plurality of divided segments; selecting one or more compared segments to check analyzed results of selected segments; and locating the selected segments in the simulated differential signal paths, and generating analyzed information comprising analyzed results of the selected segments. A related system is also disclosed.

Abstract translation: 用于分析差分信号路径中的长度差的方法包括：从存储设备（9）加载差分信号路径的设计文件; 基于设计文件模拟差分信号路径; 通过示出阻抗不连续性的阻抗分割位置将模拟差分信号路径分割成多个段; 预先定义每个分割段的可接受长度差异限制，以及计算每个分割段的实际长度差; 将实际长度差与可接受的长度差极限相对应地对应地生成对应于多个分割段的多个分析结果; 选择一个或多个比较的段以检查所选段的分析结果; 以及将所选择的段定位在所述模拟的差分信号路径中，以及生成包括所选段的分析结果的分析信息。 还公开了相关系统。

公开(公告)号：US20070076580A1

公开(公告)日：2007-04-05

申请号：US11309265

申请日：2006-07-21

Applicant: SHOU-KUO HSU ,  CHENG-SHIEN LI

Inventor： SHOU-KUO HSU ,  CHENG-SHIEN LI

IPC: H04J3/10

CPC classification number: H05K1/0246 ,  G06F13/4086 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

Abstract: An exemplary signal transmitting circuit includes a driving circuit, a main transmission line, a resistor, a node and a plurality of receiving circuits. The driving circuit is coupled to the node via the resistor and the main transmission line. Each of the receiving circuits is coupled to the node via an offshoot transmission line. The lengths of the offshoot transmission lines are generally equal to each other. It is of advantage that the signal transmitting circuit reduces signal reflections and maintains signal integrity.

Abstract translation: 示例性信号发送电路包括驱动电路，主传输线，电阻器，节点和多个接收电路。 驱动电路通过电阻和主传输线耦合到节点。 每个接收电路经由分支传输线耦合到节点。 分支传输线的长度通常彼此相等。 信号传输电路有利于减少信号反射并维持信号完整性。

公开(公告)号：US20070076498A1

公开(公告)日：2007-04-05

申请号：US11309533

申请日：2006-08-18

Applicant: DUEN-YI HO ,  SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： DUEN-YI HO ,  SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: G11C7/02

CPC classification number: G06F1/08

Abstract: A controlling circuit for automatically adjusting clock frequency of a CPU is provided. The controlling circuit includes: a current sensing circuit for converting a current signal of the CPU to a voltage signal; a voltage amplifying circuit for amplifying the voltage signal; a multi-stage switching circuit for converting the amplified voltage signal to switched signals; and a priority decoding circuit decoding the switched signals, the decoded switched signals being input to a clock generator of the CPU, and thereby adjusting the clock frequency of the CPU to fit different load on the CPU.

Abstract translation: 提供了一种用于自动调整CPU时钟频率的控制电路。 控制电路包括：电流检测电路，用于将CPU的当前信号转换成电压信号; 用于放大电压信号的电压放大电路; 用于将放大的电压信号转换成开关信号的多级切换电路; 以及对切换信号进行解码的优先解码电路，解码的开关信号被输入到CPU的时钟发生器，从而调整CPU的时钟频率以适应CPU上的不同负载。

公开(公告)号：US20130070410A1

公开(公告)日：2013-03-21

申请号：US13271803

申请日：2011-10-12

Applicant: YUNG-CHIEH CHEN ,  SHOU-KUO HSU ,  CHIH-CHUNG SHIH ,  HSIEN-CHUAN LIANG ,  WEI-CHIEH CHOU ,  CHUN-HSIEN TSAI

Inventor： YUNG-CHIEH CHEN ,  SHOU-KUO HSU ,  CHIH-CHUNG SHIH ,  HSIEN-CHUAN LIANG ,  WEI-CHIEH CHOU ,  CHUN-HSIEN TSAI

IPC: H05K7/02

CPC classification number: G06F1/185

Abstract: A computer system includes a motherboard with first and second storage device interfaces and first to third memory slots, and first to third serial advanced technology attachment dual-in-line memory modules (SATA DIMMs). First and second extending boards are extended from two opposite ends of each SATA DIMM, arranged with first and second edge connectors, respectively. The first edge connector of the first SATA DIMM is connected to the first storage device interface. The second edge connector of the first SATA DIMM is connected to the first edge connector of the second SATA DIMM. The second edge connector of the second SATA DIMM is connected to the first edge connector of the third SATA DIMM. The second edge connector of the third SATA DIMM is connected to the second storage device interface.

Abstract translation: 计算机系统包括具有第一和第二存储设备接口和第一至第三存储器插槽的主板，以及第一至第三串行高级技术附件双列直插存储器模块（SATA DIMM）。 第一和第二延伸板分别从每个SATA DIMM的两个相对端延伸，分别布置有第一和第二边缘连接器。 第一个SATA DIMM的第一个边缘连接器连接到第一个存储设备接口。 第一个SATA DIMM的第二个边缘连接器连接到第二个SATA DIMM的第一个边缘连接器。 第二个SATA DIMM的第二个边缘连接器连接到第三个SATA DIMM的第一个边缘连接器。 第三个SATA DIMM的第二个边缘连接器连接到第二个存储设备接口。

公开(公告)号：US20130067254A1

公开(公告)日：2013-03-14

申请号：US13484287

申请日：2012-05-31

Applicant: HSIEN-CHUAN LIANG ,  CHIH-CHUNG SHIH ,  SHOU-KUO HSU ,  YUNG-CHIEH CHEN

Inventor： HSIEN-CHUAN LIANG ,  CHIH-CHUNG SHIH ,  SHOU-KUO HSU ,  YUNG-CHIEH CHEN

IPC: G06F1/26

CPC classification number: G06F1/266 ,  G06F1/30 ,  G06F11/1443

Abstract: In a method for transmitting data between a host computer and a slave device, the host computer connects to a slave device through a data communication port. The slave device is equipped with a power supply that includes at least one capacitor. The power supply is charged through the host computer using the capacitor when the host computer is powered on. The method controls the host computer sends data to the slave device, and controls the capacitor to discharge to provide power to the slave device for a period of time when the host computer is powered off, and stores the data packet into the slave device during the period of time. The method further retrieves the data from the storage device when the host computer is powered on, and resends the data to the slave device through the data communication port.

Abstract translation: 在主计算机和从设备之间传输数据的方法中，主计算机通过数据通信端口连接到从设备。 从设备配备有包括至少一个电容器的电源。 当主机上电时，电源通过主机使用电容充电。 该方法控制主计算机向从设备发送数据，并控制电容器放电，以在主机断电的时间段内向从设备供电，并在数据包存储期间将数据包存储在从设备中 一段的时间。 当主计算机通电时，该方法还从存储设备检索数据，并通过数据通信端口将数据重新发送到从设备。

公开(公告)号：US20120327623A1

公开(公告)日：2012-12-27

申请号：US13596066

申请日：2012-08-28

Applicant: YUNG-CHIEH CHEN ,  CHENG-HSIEN LI ,  SHOU-KUO HSU

Inventor： YUNG-CHIEH CHEN ,  CHENG-HSIEN LI ,  SHOU-KUO HSU

IPC: H01R4/00 ,  H05K3/32

CPC classification number: H05K1/0295 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/113 ,  H05K2201/09236 ,  H05K2201/09954 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: A printed circuit board includes first and second layout layers, first and second components, and a pair of connecting portions. The first layout layer includes a pair of first conducting portions connected to a control chip. The second layout layer includes pairs of second to fourth conducting portions. The connecting portions connect the first and third conducting portions together. When an electronic device is connected to the second conducting portions, and the first and second components are connected to the third and fourth conducting portions to form a first route, signals generated by the control chip are transmitted to the electronic device through the first route. When the electronic device is connected to the fourth conducting portions, and the first and second components are connected to the second and third conducting portions to form a second route, the signals are transmitted to the electronic device through the second route.

Abstract translation: 印刷电路板包括第一和第二布局层，第一和第二部件以及一对连接部分。 第一布局层包括连接到控制芯片的一对第一导电部分。 第二布局层包括成对的第二至第四导电部分。 连接部分将第一和第三导电部分连接在一起。 当电子设备连接到第二导电部分，并且第一和第二部件连接到第三和第四导电部分以形成第一路由时，由控制芯片产生的信号通过第一路径传输到电子设备。 当电子设备连接到第四导电部分，并且第一和第二部件连接到第二和第三导电部分以形成第二路线时，信号通过第二路径传输到电子设备。

公开(公告)号：US20120320518A1

公开(公告)日：2012-12-20

申请号：US13172603

申请日：2011-06-29

Applicant: YUNG-CHIEH CHEN ,  SHOU-KUO HSU

Inventor： YUNG-CHIEH CHEN ,  SHOU-KUO HSU

IPC: G06F1/16

CPC classification number: G06F1/185

Abstract: A serial advanced technology attachment (SATA) DIMM includes a board body. A control chip is arranged on the board body. An extending board extends from an end of the board body. A first edge connector is set on the extending board. A second edge connector is set on a bottom side of the board body. The first edge connector includes a number of signal pins connected to the control chip, and a number of ground pins.

Abstract translation: 串行高级技术附件（SATA）DIMM包括板体。 控制芯片布置在板体上。 延伸板从板体的端部延伸。 第一边缘连接器设置在延伸板上。 第二边缘连接器设置在电路板主体的底侧。 第一边缘连接器包括连接到控制芯片的多个信号引脚和多个接地引脚。

公开(公告)号：US20120174054A1

公开(公告)日：2012-07-05

申请号：US13214256

申请日：2011-08-22

Applicant: SHIN-TING YEN ,  SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  DAN-CHEN WU

Inventor： SHIN-TING YEN ,  SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  DAN-CHEN WU

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/74

Abstract: A computing system includes a drawing unit and a layout unit. The computing system sets components parameters to components of a circuit diagram of a printed circuit board (PCB). The drawing unit draws the circuit diagram by using the components with the components parameters. If the drawing unit wants to use a component more than once, the computing system copies the component and the corresponding components parameters. The drawing unit uses the copied components and the corresponding parameters. If the circuit diagram has been drawn, the layout unit loads the circuit diagram and wires the PCB according to the components and the components parameters in the circuit diagram.

Abstract translation: 计算系统包括绘图单元和布局单元。 计算系统将组件参数设置为印刷电路板（PCB）的电路图的组件。 绘图单元通过使用具有组件参数的组件绘制电路图。 如果绘图单元想要多次使用组件，则计算系统将复制组件和相应的组件参数。 绘图单元使用复制的组件和相应的参数。 如果绘制了电路图，布局单元将根据电路图中的组件和组件参数加载电路图并连接PCB。