公开(公告)号：US20200091943A1

公开(公告)日：2020-03-19

申请号：US16694205

申请日：2019-11-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

IPC: H03M13/00 ,  H03M13/27 ,  G06F9/38

Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.

公开(公告)号：US20190095205A1

公开(公告)日：2019-03-28

申请号：US16203528

申请日：2018-11-28

Applicant: Texas Instruments Incorporated

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/30 ,  G06F11/00 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F12/0897 ,  G06F9/32 ,  G06F12/0875

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：USRE46193E1

公开(公告)日：2016-11-01

申请号：US14303262

申请日：2014-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Lewis Nardini ,  Jose Luis Flores ,  Abhijeet Chachad ,  Raguram Damodaran ,  Joseph R. M. Zbiciak ,  Gary Swoboda

IPC: G06F1/32

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract translation: 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

公开(公告)号：US20250156186A1

公开(公告)日：2025-05-15

申请号：US19027541

申请日：2025-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F7/499 ,  G06F9/38 ,  G06F15/80

Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

公开(公告)号：US20250156185A1

公开(公告)日：2025-05-15

申请号：US19027028

申请日：2025-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Asheesh Bhardwaj ,  Timothy David Anderson ,  Son Hung Tran

IPC: G06F9/30 ,  G06F7/74 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897 ,  G06F17/16

Abstract: Software instructions are executed on a processor within a computer system to configure a streaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.

公开(公告)号：US20250094358A1

公开(公告)日：2025-03-20

申请号：US18966252

申请日：2024-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

公开(公告)号：US12217054B2

公开(公告)日：2025-02-04

申请号：US17946113

申请日：2022-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang Bui ,  Alan L. Davis ,  Dheera Balasubramanian Samudrala ,  Timothy David Anderson

IPC: G06F9/30 ,  G06F9/38

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

公开(公告)号：US12216591B2

公开(公告)日：2025-02-04

申请号：US18477674

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

公开(公告)号：US20250028645A1

公开(公告)日：2025-01-23

申请号：US18907746

申请日：2024-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0891 ,  G06F12/1027

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

公开(公告)号：US12189540B2

公开(公告)日：2025-01-07

申请号：US18456619

申请日：2023-08-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/12 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.