公开(公告)号：US20230076806A1

公开(公告)日：2023-03-09

申请号：US17981608

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11578

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11569264B2

公开(公告)日：2023-01-31

申请号：US17122228

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11556

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

公开(公告)号：US11569251B2

公开(公告)日：2023-01-31

申请号：US16535431

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu

IPC: H01L27/11526 ,  H01L29/49 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L21/265

Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

公开(公告)号：US20220406606A1

公开(公告)日：2022-12-22

申请号：US17397632

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

公开(公告)号：US11527553B2

公开(公告)日：2022-12-13

申请号：US17140888

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/417 ,  H01L27/11585 ,  H01L27/11587

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US20220367517A1

公开(公告)日：2022-11-17

申请号：US17874844

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11578

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11488971B2

公开(公告)日：2022-11-01

申请号：US17104686

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

公开(公告)号：US20220278130A1

公开(公告)日：2022-09-01

申请号：US17744212

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1159

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US11424339B2

公开(公告)日：2022-08-23

申请号：US17081012

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chia-En Huang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3215 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.

公开(公告)号：US11355516B2

公开(公告)日：2022-06-07

申请号：US17018232

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.