公开(公告)号：US11714131B1

公开(公告)日：2023-08-01

申请号：US17699900

申请日：2022-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Shiv Kumar Vats ,  Umesh Chandra Srivastava

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318533 ,  G01R31/318552 ,  G01R31/3177 ,  G01R31/31725

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

公开(公告)号：US20230231546A1

公开(公告)日：2023-07-20

申请号：US18151332

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Aradhana KUMARI

IPC: H03K5/1252 ,  H03K5/135

CPC classification number: H03K5/1252 ,  H03K5/135

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.

公开(公告)号：US20230206032A1

公开(公告)日：2023-06-29

申请号：US18172979

申请日：2023-02-22

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Giuseppe DESOLI ,  Carmine CAPPETTA ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Saumya SUNEJA

IPC: G06N3/045 ,  G06F16/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/045 ,  G06F16/2282 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/217

Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

公开(公告)号：US11687762B2

公开(公告)日：2023-06-27

申请号：US16280991

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F17/17 ,  G06N20/00 ,  G06F1/26 ,  G06F17/16 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F1/26 ,  G06F17/16 ,  G06F17/175 ,  G06N3/045 ,  G06N3/08 ,  G06N20/00

Abstract: Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.

公开(公告)号：US11687428B2

公开(公告)日：2023-06-27

申请号：US17152901

申请日：2021-01-20

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: G06F11/00 ,  G06F11/263 ,  G06F1/06 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F1/06 ,  G06F11/2236

Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.

公开(公告)号：US20230186983A1

公开(公告)日：2023-06-15

申请号：US18167580

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY ,  Nitin CHAWLA

IPC: G11C11/419 ,  H10B10/00

CPC classification number: G11C11/419 ,  H10B10/12

Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.

公开(公告)号：US20230168699A1

公开(公告)日：2023-06-01

申请号：US17967498

申请日：2022-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Dhulipalla Phaneendra Kumar ,  Gourav Garg ,  Sourabh Banzal

IPC: G05F1/46 ,  H03K19/20

CPC classification number: G05F1/46 ,  H03K19/20

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

公开(公告)号：US11665915B2

公开(公告)日：2023-05-30

申请号：US16863856

申请日：2020-04-30

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Fabio De Santis ,  Vikas Rana

IPC: H01L27/105 ,  H01L27/11521 ,  H01L27/112 ,  G11C29/00 ,  H01L27/11519 ,  H01L27/11558 ,  G11C16/04 ,  H01L21/66

CPC classification number: H01L27/1052 ,  G11C29/006 ,  H01L27/1122 ,  H01L27/1124 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  G11C16/0433 ,  H01L22/00

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US11646741B2

公开(公告)日：2023-05-09

申请号：US17931043

申请日：2022-09-09

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Prashutosh Gupta ,  Ankit Gupta

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0812 ,  H03L7/085

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

公开(公告)号：US11615823B2

公开(公告)日：2023-03-28

申请号：US17542203

申请日：2021-12-03

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vivek Tyagi ,  Vikas Rana ,  Chantal Auricchio ,  Laura Capecchi

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.