公开(公告)号：US08212701B2

公开(公告)日：2012-07-03

申请号：US12988265

申请日：2009-04-16

Applicant: Andreia Cathelin ,  Axel Flament ,  Andreas Kaiser

Inventor： Andreia Cathelin ,  Axel Flament ,  Andreas Kaiser

IPC: H03M3/00

CPC classification number: H04B1/0483 ,  H03F3/2175 ,  H03F3/602

Abstract: An integrated circuit includes input circuitry for receiving a radio frequency digital signal, output circuitry capable of delivering a radio frequency analog signal, and a processing stage coupled between the input circuitry and the output circuitry and including several processing channels in parallel. Each processing channel may include a voltage switching block the input of which is coupled to the input circuitry and a transmission line substantially of the quarter-wave type at the frequency of the radio frequency analog signal coupled in series between the output of the voltage switching block and the output circuitry.

Abstract translation: 集成电路包括用于接收射频数字信号的输入电路，能够传送射频模拟信号的输出电路，以及耦合在输入电路和输出电路之间的处理级并且包括若干并行的处理通道。 每个处理通道可以包括其输入端耦合到输入电路的电压切换模块和基本上四分之一波型的传输线，其中射频模拟信号的频率串联耦合在电压切换模块 和输出电路。

公开(公告)号：US20120153997A1

公开(公告)日：2012-06-21

申请号：US13242508

申请日：2011-09-23

Applicant: Jean-Pierre Blanc ,  Pratap Narayan Singh

Inventor： Jean-Pierre Blanc ,  Pratap Narayan Singh

IPC: H03B1/00

CPC classification number: G05F3/30

Abstract: A circuit for generating a reference voltage including: a first current source in series with a first bipolar transistor, between a first and a second terminal of application of a power supply voltage; a second current source in series with a second bipolar transistor and a first resistive element, between said first and second terminals, the junction point of the first resistive element and of the second bipolar transistor defining a third terminal for providing the reference voltage; a follower assembly having an input terminal connected between the first current source and the first bipolar transistor, and having an output terminal connected to a base of the second bipolar transistor; and a resistive dividing bridge between the output terminal of the follower assembly and said second terminal, the midpoint of this dividing bridge being connected to a base of the first bipolar transistor.

Abstract translation: 一种用于产生参考电压的电路，包括：与第一双极晶体管串联的第一电流源，在施加电源电压的第一和第二端子之间; 与所述第一和第二端子之间的第二双极晶体管和第一电阻元件串联的第二电流源，所述第一电阻元件和所述第二双极晶体管的结点限定用于提供参考电压的第三端子; 跟随器组件，其具有连接在第一电流源和第一双极晶体管之间的输入端子，并且具有连接到第二双极晶体管的基极的输出端子; 以及在从动组件的输出端子和所述第二端子之间的电阻分压桥，该分隔桥的中点连接到第一双极晶体管的基极。

公开(公告)号：US08183517B2

公开(公告)日：2012-05-22

申请号：US12798977

申请日：2010-04-15

Applicant: Francois Roy ,  Thomas Girault

Inventor： Francois Roy ,  Thomas Girault

IPC: G02B27/10

CPC classification number: H01L27/14625 ,  G02B6/12004 ,  G02B6/1228 ,  G02B6/136 ,  G02B6/4298 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14685

Abstract: An integrated circuit having a photosensitive cell with an entry face, a photosensitive element and at least two elements forming a light guide and placed between the entry face and the photosensitive element. The second element is located between the first element and the entry face such that the two elements guide the light coming from the entry face onto the photosensitive element and each element forms a light guide. The inner volume has a first surface located on the same side as the photosensitive element, a second surface located on the same side as the entry face, and a lateral surface joining said first surface to said second surface and separating the inner volume from the outer volume. The first surface of the inner volume of the second element has a smaller area than that of the second surface of the inner volume of the first element.

Abstract translation: 一种集成电路，其具有具有入射面的感光单元，感光元件和至少两个元件，形成光导并且放置在入射面和感光元件之间。 第二元件位于第一元件和入口面之间，使得两个元件将来自入口面的光引导到感光元件上，并且每个元件形成光导。 内部体积具有位于与感光元件相同侧的第一表面，位于与入射面相同侧的第二表面，以及将所述第一表面连接到所述第二表面的侧表面，并将内部体积与外部 卷。 第二元件的内部体积的第一表面具有比第一元件的内部容积的第二表面的面积小的面积。

公开(公告)号：US08174533B2

公开(公告)日：2012-05-08

申请号：US11766460

申请日：2007-06-21

Applicant: Patrice Couvert ,  Anthony Philippe

Inventor： Patrice Couvert ,  Anthony Philippe

IPC: G06F12/00

CPC classification number: G06T1/60 ,  G06F9/345 ,  G06F9/3552 ,  H04N19/433 ,  H04N19/51

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract translation: 系统包括存储与图像中的像素相关联的地址的数据的存储器，每个地址通过函数被连接到有序图像参考帧中的像素的坐标，用于处理与像素相关联的数据的设备，其中处理像素 由关联的向量相对于参考像素引用，以及向处理设备提供数据的接口设备。 数据请求指示与正在处理的像素相关联的向量。 参考像素的坐标通过将函数应用于与参考像素相关联的地址来确定。 接下来，基于参考像素的坐标和向量来获得正在处理的像素的坐标。 然后，通过将函数的反函数应用于正在处理的像素的坐标来确定与正在处理的像素相关联的数据的地址。

公开(公告)号：US08165549B2

公开(公告)日：2012-04-24

申请号：US12208921

申请日：2008-09-11

Applicant: Andras Pozsgay ,  Frédéric Paillardet

Inventor： Andras Pozsgay ,  Frédéric Paillardet

IPC: H04B1/06 ,  H03M1/66 ,  H04L27/00

CPC classification number: H03H17/025 ,  H03M3/504

Abstract: An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.

Abstract translation: 电子设备包括用时钟信号操作并具有输出电路以输送数字数据信号的Σ-Δ调制电路。 第一个电路传送一个射频转置信号。 陷波滤波器包括射频数模转换块，其具有耦合到输出电路的第一输入电路。 第二输入电路接收射频转置信号。 第二输出电路提供射频模拟信号。 数字延迟电路由时钟信号控制，并且包括两个第一输入电路之间的延迟块。 陷波滤波器的陷波的频率与延迟块的延迟值有关。 求和电路对射频信号进行求和。

公开(公告)号：US20120074527A1

公开(公告)日：2012-03-29

申请号：US13230035

申请日：2011-09-12

Applicant: Fabrice Casset ,  Lionel Cadix ,  Perceval Coudrain ,  Alexis Farcy ,  Laúrent-Lüc Chapelon ,  Yacine Felk ,  Pascal Ancey

Inventor： Fabrice Casset ,  Lionel Cadix ,  Perceval Coudrain ,  Alexis Farcy ,  Laúrent-Lüc Chapelon ,  Yacine Felk ,  Pascal Ancey

IPC: H01L29/06 ,  H01L21/283

CPC classification number: B81C1/00246 ,  B81B2201/014 ,  B81B2201/0235 ,  B81B2201/0271 ,  B81B2203/0353 ,  B81B2207/012 ,  B81C1/005 ,  G01P15/125 ,  G01P2015/082 ,  H01L2924/0002 ,  H03H3/0073 ,  H03H9/2426 ,  H01L2924/00

Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.

Abstract translation: 集成电路包括具有相对的第一和第二主表面的支撑基板。 空腔通过支撑基板并连接第一和第二主表面。 集成电路包括具有移动元件的装置，移动元件和一对相关联的电极包括在空腔中。 移动元件的锚定节点位于第一主表面的水平面上。 集成电路包括布置在第一主表面的电平处的第一基本芯片，并与移动元件电连接到该装置。

公开(公告)号：US20120062313A1

公开(公告)日：2012-03-15

申请号：US13232529

申请日：2011-09-14

Applicant: Julien LE COZ ,  Alexandre Valentian ,  Philippe Flatresse ,  Sylvain Engels

Inventor： Julien LE COZ ,  Alexandre Valentian ,  Philippe Flatresse ,  Sylvain Engels

IPC: G05F3/02

CPC classification number: G05F3/205 ,  H03K19/0013

Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Abstract translation: MOS功率晶体管的衬底的动态偏置电路可以包括第一开关，其被配置为当晶体管的栅极电压使晶体管导通时，将衬底连接到电流源，该电流源向前偏置晶体管的本征源极 - 衬底二极管 。 电流源可以包括与衬底和电源电压之间的本征二极管相同的导通方向的二极管堆叠。

公开(公告)号：US20110246811A1

公开(公告)日：2011-10-06

申请号：US13074204

申请日：2011-03-29

Applicant: Josep Torras Flaquer ,  Jean-Marc Daveau ,  Lirida Naviner ,  Philippe Roche

Inventor： Josep Torras Flaquer ,  Jean-Marc Daveau ,  Lirida Naviner ,  Philippe Roche

IPC: G06F11/00

CPC classification number: G06F11/008 ,  G06F17/50 ,  G06F2217/10

Abstract: The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.

Abstract translation: 确定具有包括相关源和信宿之间的至少一个再会聚路径的分量节点网络的电子电路的可靠性指南涉及路径的每个分量的水平，条件概率矩阵的计算，其条件概率矩阵的调节 与位于组件上游的路径的至少一个节点相关。

公开(公告)号：US08030712B2

公开(公告)日：2011-10-04

申请号：US12625418

申请日：2009-11-24

Applicant: Olivier Le Neel ,  Olivier Girard ,  Fabio Ferrari

Inventor： Olivier Le Neel ,  Olivier Girard ,  Fabio Ferrari

IPC: H01L27/11

CPC classification number: H01L21/32136 ,  H01L27/0629

Abstract: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.

Abstract translation: 用于保护半导体衬底上的电路部件的等离子体蚀刻或其它去除工艺的方法包括在辅助层上形成屏蔽层，以隐藏至少覆盖电路部件的至少一部分的辅助层的区域， 例如高欧姆多晶硅电阻器。 该方法通过根据图案选择性地去除屏蔽层的部分，将由掩模限定的图案转印到筛选层上。 辅助层的不受屏蔽层保护的部分使用对辅助层材料选择性的等离子体气体来去除，而不去除覆盖电路部件部分的辅助层的区域，从而保护电路部件免受 等离子体气体通过屏蔽层和辅助层。

公开(公告)号：US07993796B2

公开(公告)日：2011-08-09

申请号：US11317436

申请日：2005-12-22

Applicant: Mathieu Roy ,  Fabien Pierre

Inventor： Mathieu Roy ,  Fabien Pierre

IPC: H01M8/04 ,  H01M8/08 ,  H01M4/02 ,  H01M4/36 ,  H01M4/62

CPC classification number: B82Y30/00 ,  H01L21/76898 ,  H01L2221/1094 ,  H01M4/926 ,  H01M8/0234 ,  H01M8/1007 ,  H01M8/1097 ,  Y02P70/56 ,  Y10T428/24273 ,  Y10T428/249955 ,  Y10T428/249975

Abstract: A thin wafer comprising through holes filled at least partially with conductive carbon nanotubes generally oriented transversally to the wafer. A fuel cell comprising, in a thin wafer, a through hole filled with an electrolyte surrounded with barriers of carbon nanotubes generally oriented transversally to the wafer.

Abstract translation: 包括至少部分地填充有通常横向于晶片定向的导电碳纳米管的通孔的薄晶片。 一种燃料电池，其在薄晶片中包括填充有电解质的通孔，所述电解质围绕着通常横向于所述晶片的碳纳米管的屏障。