公开(公告)号：US07781850B2

公开(公告)日：2010-08-24

申请号：US11090911

申请日：2005-03-25

Applicant: Mark W. Miles ,  John Batey ,  Clarence Chui ,  Manish Kothari ,  Ming-Hau Tung

Inventor： Mark W. Miles ,  John Batey ,  Clarence Chui ,  Manish Kothari ,  Ming-Hau Tung

IPC: H01L27/14

CPC classification number: B81B3/0086 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2201/053 ,  G02B26/001

Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Abstract translation: 在一个实施例中，本发明提供一种用于制造微机电系统装置的方法。 该方法包括制造包括具有特征机电响应的膜的第一层和特征光学响应，其中特征光学响应是期望的，并且特征机电响应是不期望的; 以及通过在所述微机电系统装置的启动期间至少减少其上的电荷积累来修改所述第一层的特征机电响应。

公开(公告)号：US07666702B2

公开(公告)日：2010-02-23

申请号：US11946831

申请日：2007-11-28

Applicant: Sheng-Hung Li ,  Siew-Seong Tan ,  Cheng-Yen Liu ,  Li-Ken Yeh

Inventor： Sheng-Hung Li ,  Siew-Seong Tan ,  Cheng-Yen Liu ,  Li-Ken Yeh

IPC: H01L21/00 ,  H01L21/4763 ,  G02B26/00

CPC classification number: B81C1/00801 ,  B81C2201/0107 ,  B81C2201/014

Abstract: A method for fabricating a microstructure is to form at least one insulation layer including a micro-electro-mechanical structure therein over an upper surface of a silicon substrate. The micro-electro-mechanical structure includes at least one microstructure and a metal sacrificial structure that are independent with each other. In the metal sacrificial structure are formed a plurality of metal layers and a plurality of metal via layers connected to the respective metal layers. A barrier layer is formed over an upper surface of the insulation layer, and an etching stop layer is subsequently formed over a lower surface of the silicon substrate. An etching operation is carried out from the lower surface of the silicon substrate to form a space corresponding to the micro-electro-mechanical structure, and then the metal sacrificial structure is etched, thus achieving a microstructure suspension.

Abstract translation: 用于制造微结构的方法是在硅衬底的上表面上形成包括微​​电子机械结构的至少一个绝缘层。 微电子机械结构包括彼此独立的至少一个微结构和金属牺牲结构。 在金属牺牲结构中形成多个金属层和连接到各个金属层的多个金属通孔层。 在绝缘层的上表面上形成阻挡层，随后在硅衬底的下表面上形成蚀刻停止层。 从硅衬底的下表面进行蚀刻操作以形成与微电子机械结构相对应的空间，然后蚀刻金属牺牲结构，从而实现微结构悬浮。

公开(公告)号：US20100038731A1

公开(公告)日：2010-02-18

申请号：US12441254

申请日：2006-11-02

Applicant: Robertus P. Van Kampen ,  Robert Kazinczi

Inventor： Robertus P. Van Kampen ,  Robert Kazinczi

IPC: H01L29/84 ,  H01L21/3205

CPC classification number: H01H59/0009 ,  B81C1/0015 ,  B81C2201/014 ,  B81C2201/0176 ,  G11C23/00 ,  H01H51/12

Abstract: A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever (101) over at least a portion of the first layer of sacrificial material. The third step is depositing, by use of Atomic Layer Deposition, a second layer of sacrificial material over the first layer of sacrificial material and over a portion of the cantilever such that a portion of the cantilever is surrounded by sacrificial material. The fourth step is providing a further layer material (107) which covers at least a portion of the second layer of sacrificial material. Finally, the last step is etching away the sacrificial material surrounding the cantilever, thereby defining a cavity (102) in which the cantilever is suspended.

Abstract translation: 一种非易失性存储器件和制造非易失性微机电存储单元的方法。 该方法包括通过使用原子层沉积在衬底上沉积第一层牺牲材料的第一步骤。该方法的第二步是在第一层牺牲材料的至少一部分上提供悬臂（101）。 第三步骤是通过使用原子层沉积在第一层牺牲材料上并在悬臂的一部分上沉积第二层牺牲材料，使得悬臂的一部分被牺牲材料包围。 第四步是提供覆盖牺牲材料的第二层的至少一部分的另外的层材料（107）。 最后，最后一步是蚀刻掉围绕悬臂的牺牲材料，由此限定悬臂悬挂在其中的空腔（102）。

公开(公告)号：US20100025786A1

公开(公告)日：2010-02-04

申请号：US12086951

申请日：2006-11-15

Applicant: Peter Schmollngruber ,  Hans Artmann ,  Thomas Wagner ,  Heribert Weber

Inventor： Peter Schmollngruber ,  Hans Artmann ,  Thomas Wagner ,  Heribert Weber

IPC: H01L29/84 ,  H01L21/30

CPC classification number: B81C1/00158 ,  B81B3/0081 ,  B81C2201/014

Abstract: A method for manufacturing a diaphragm, on a semiconductor substrate, includes the method operations or tasks of a) providing a semiconductor substrate, b) producing trenches in the semiconductor substrate, webs made of semiconductor substrate remaining between the trenches, c) producing an oxide layer on the walls of the trenches with the aid of a thermal oxidation method, d) producing access openings in a cover layer produced in a preceding method operation or task on the semiconductor substrate, to expose the semiconductor substrate in the area of the webs, e) isotropic etching of the semiconductor substrate exposed in method operation or task d) using a method selective to the oxide layer and to the cover layer, at least one cavity being produced in the webs below the cover layer, which is laterally delimited by the oxide layer of at least one trench, and f) depositing a sealing layer to seal the access openings in the cover layer.

Abstract translation: 一种在半导体衬底上制造隔膜的方法包括以下方法操作或任务：a）提供半导体衬底，b）在半导体衬底中制造沟槽，保留在沟槽之间的由半导体衬底制成的网，c）产生氧化物 借助于热氧化方法在沟槽的壁上形成层; d）在半导体衬底上的前述方法操作或任务中产生的覆盖层中产生进入开口，以在幅材的区域中露出半导体衬底， e）在方法操作或任务中暴露的半导体衬底的各向同性蚀刻d）使用对氧化物层和覆盖层选择性的方法，在覆盖层下方的纤维网中产生至少一个空腔， 氧化物层，以及f）沉积密封层以密封覆盖层中的进入开口。

公开(公告)号：US20090317931A1

公开(公告)日：2009-12-24

申请号：US12488882

申请日：2009-06-22

Applicant: François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

Inventor： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

IPC: H01L29/84

CPC classification number: B81C1/00238 ,  B81B2201/0271 ,  B81C1/00357 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/0191

Abstract: The invention relates to a method of fabricating an electromechanical device including an active element, wherein the method comprises the following steps:a) making a monocrystalline first stop layer on a monocrystalline layer of a first substrate;b) growing a monocrystalline mechanical layer epitaxially on said first stop layer out of at least one material that is different from that of the stop layer;c) making a sacrificial layer on said active layer out of a material that is suitable for being etched selectively relative to said mechanical layer;d) making a bonding layer on the sacrificial layer;e) bonding a second substrate on the bonding layer; andf) eliminating the first substrate and the stop layer to reveal the surface of the mechanical layer opposite from the sacrificial layer, the active element being made by at least a portion of the mechanical layer.

Abstract translation: 本发明涉及一种制造包括有源元件的机电装置的方法，其中该方法包括以下步骤：a）在第一衬底的单晶层上制备单晶第一阻挡层; b）在所述第一停止层上外延生长至少一种不同于所述停止层的材料的单晶机械层; c）在适合于相对于所述机械层选择性蚀刻的材料中在所述有源层上制造牺牲层; d）在牺牲层上形成结合层; e）在接合层上粘合第二衬底; 以及f）消除所述第一衬底和所述阻挡层以露出与所述牺牲层相对的所述机械层的表面，所述有源元件由所述机械层的至少一部分制成。

公开(公告)号：US20090243004A1

公开(公告)日：2009-10-01

申请号：US12056286

申请日：2008-03-27

Applicant: Bang-Chiang Lan ,  Li-Hsun Ho ,  Wei-Cheng Wu ,  Hui-Min Wu ,  Min Chen ,  Tzung-I Su ,  Chien-Hsin Huang

Inventor： Bang-Chiang Lan ,  Li-Hsun Ho ,  Wei-Cheng Wu ,  Hui-Min Wu ,  Min Chen ,  Tzung-I Su ,  Chien-Hsin Huang

IPC: H01L29/84 ,  H01L21/00

CPC classification number: B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0792 ,  H01L27/0688

Abstract: The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping device is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping device has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.

Abstract translation: 本发明涉及用于MEMS器件和半导体器件的集成结构及其制造方法，其中在MEMS器件和半导体器件之间的衬底上包括蚀刻停止器件，用于保护半导体器件免受横向 执行氧化物释放处理以制造MEMS器件时的损坏。 蚀刻停止装置具有各种形状，并且通过单独的制造工艺选择性地形成，或者在相同的制造工艺中与半导体器件同时形成。 它是单一结构或组合堆叠的多层结构，例如多排支撑的耐蚀刻材料插塞，一个或多个壁状耐蚀刻材料插塞或其堆叠的多层结构 和耐蚀刻材料层。

公开(公告)号：US20090166772A1

公开(公告)日：2009-07-02

申请号：US11967261

申请日：2007-12-31

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee

IPC: H01L29/84 ,  H01L21/00

CPC classification number: B81C1/00182 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate.

Abstract translation: 微电子机械系统（MEMS）装置包括背板基板，其具有形成有多个穿孔的预期区域。 布置在所述背板基板上的第一结构介电层，其中所述电介质层具有在所述预定区域上方的开口。 设置在第一结构介电层上的蚀刻停止层。 形成在背板基板上的第二结构介电层。 蚀刻停止层和第二结构介电层形成微机隔膜的至少一部分，并且覆盖在第一结构介电层的开口上，以在微机隔膜和背板基板之间形成室。

公开(公告)号：US20090049911A1

公开(公告)日：2009-02-26

申请号：US12285660

申请日：2008-10-10

Applicant: Hiroshi Fukuda ,  Tsukasa Fujimori ,  Natsuki Yokohama ,  Yuko Hanaoka ,  Takafumi Matsumura

Inventor： Hiroshi Fukuda ,  Tsukasa Fujimori ,  Natsuki Yokohama ,  Yuko Hanaoka ,  Takafumi Matsumura

IPC: G01P15/125

CPC classification number: B81C1/00246 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742

Abstract: In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.

公开(公告)号：US07344994B2

公开(公告)日：2008-03-18

申请号：US11063108

申请日：2005-02-22

Applicant: John W. Krawczyk ,  Andrew L. McNees ,  Christopher J. Money ,  Girish S. Patil ,  David B. Rhine ,  Karthik Vaideeswaran

Inventor： John W. Krawczyk ,  Andrew L. McNees ,  Christopher J. Money ,  Girish S. Patil ,  David B. Rhine ,  Karthik Vaideeswaran

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0332 ,  B81B2203/0353 ,  B81C1/00531 ,  B81C1/00619 ,  B81C2201/0132 ,  B81C2201/014 ,  H01L21/0334 ,  H01L21/3081 ,  H01L21/3083

Abstract: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop material. The first layer is a relatively soft etch stop material. A second layer is applied to the first layer on the back side of the substrate to provide a composite etch stop layer. The second layer is a relatively hard etch stop material. The substrate is etched from a side opposite the back side of the substrate to provide a slot in the substrate.

Abstract translation: 使用深反应离子蚀刻工艺蚀刻半导体衬底以在衬底中产生通孔或槽（以下称为“槽”）的工艺。 该方法包括将第一层作为第一蚀刻停止材料施加到衬底的背面。 第一层是相对软的蚀刻停止材料。 将第二层施加到衬底的背面上的第一层以提供复合蚀刻停止层。 第二层是相对硬的蚀刻停止材料。 从与衬底的背面相对的一侧蚀刻衬底，以在衬底中提供槽。

公开(公告)号：US20080009090A1

公开(公告)日：2008-01-10

申请号：US11896171

申请日：2007-08-30

Applicant: Makoto Asai

Inventor： Makoto Asai

IPC: H01L21/306

CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0292 ,  B81B2203/0118 ,  B81C2201/014 ,  B81C2201/019 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

Abstract: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably supported on the substrate; and an insulation layer disposed on a bottom of the movable portion so that the insulation layer provides a roof of the cavity.

Abstract translation: 物理量传感器包括：半导体衬底; 设置在所述基板中并在所述基板的水平方向上延伸的空腔; 设置在所述基板上并到达所述空腔的凹槽; 可移动部分，由空腔和沟槽分隔开，使得可移动部分可移动地支撑在基板上; 以及设置在所述可动部分的底部上的绝缘层，使得所述绝缘层提供所述空腔的顶部。