公开(公告)号：US11372147B2

公开(公告)日：2022-06-28

申请号：US17245320

申请日：2021-04-30

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork

IPC: G02B5/30 ,  G02B5/18 ,  G02B27/46 ,  H04N5/335 ,  H01L27/146 ,  G02B27/42 ,  H04N5/232

Abstract: Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by the photodetector array. Images can be captured without a lens, and cameras can be made smaller than those that are reliant on lenses and ray-optical focusing.

公开(公告)号：US20220199132A1

公开(公告)日：2022-06-23

申请号：US17432064

申请日：2020-02-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C7/22

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

公开(公告)号：US20220190846A1

公开(公告)日：2022-06-16

申请号：US17548176

申请日：2021-12-10

Applicant: Rambus Inc.

Inventor： Michael Thomas Imel

IPC: H03M13/11 ,  H03M13/19

Abstract: An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m

公开(公告)号：US20220188249A1

公开(公告)日：2022-06-16

申请号：US17556376

申请日：2021-12-20

Applicant: Rambus Inc.

Inventor： Vlad Fruchter ,  Keith Lowery ,  George Michael Uhler ,  Steven Woo ,  Chi-Ming (Philip) Yeung ,  Ronald Lee

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

公开(公告)号：US11361839B2

公开(公告)日：2022-06-14

申请号：US17049282

申请日：2019-03-20

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Frederick A. Ware

IPC: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

公开(公告)号：US20220182267A1

公开(公告)日：2022-06-09

申请号：US17532865

申请日：2021-11-22

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Marcus van Ierssel

IPC: H04L25/49 ,  H03L7/08 ,  H04L27/06 ,  H04L7/033

Abstract: A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

公开(公告)号：US20220179556A1

公开(公告)日：2022-06-09

申请号：US17544584

申请日：2021-12-07

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Steven C. Woo ,  Thomas Vogelsang

IPC: G06F3/06

Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

公开(公告)号：US20220172760A1

公开(公告)日：2022-06-02

申请号：US17531151

申请日：2021-11-19

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/06 ,  G11C5/02 ,  G11C8/18 ,  H01L25/065 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US11349496B2

公开(公告)日：2022-05-31

申请号：US17321060

申请日：2021-05-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03M13/05 ,  G06F11/10 ,  G06F13/16 ,  G06F3/06 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H03M13/19

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

公开(公告)号：US11347665B2

公开(公告)日：2022-05-31

申请号：US16914221

申请日：2020-06-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F13/16 ,  H04L47/50 ,  G06F9/48 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.