Abstract:
A sandwich ARC structure for preventing metal to contact from shifting, the sandwich ARC structure comprising a first Ti layer formed on a metal laer and a first TiN layer formed on the first Ti layer. A second Ti layer is formed on the first TiN layer and a second TiN layer is formed on the second Ti layer. Wherein the sandwich ARC structure formed of first Ti/first TiN/second Ti/second TiN will reduces the tress between said metal layer and a dielectric layer formed below the metal layer.
Abstract:
A cooling system for a hot plate. The cooling system includes a plurality of pipelines inside the hot plate. Each pipeline has an inlet and an outlet. The inlet permits a cooling fluid to enter and the outlet permits the cooling fluid to leave. The cooling fluid running inside the pipelines picks up heat from the hot plate and carries away so that the hot plate is cooled.
Abstract:
A method comprises forming a BARC layer on a substrate, treating the BARC layer to make its surface hydrophilic, forming a photoresist layer on the treated BARC layer, exposing the photoresist layer to a predetermined pattern, and developing the photoresist layer to form patterned photoresist.
Abstract:
An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.
Abstract:
A method of forming a dual-layer resist and application thereof. With respect to the method of forming a dual-layer resist, first, a patterned first resist layer is formed on a substrate. Next, the first resist layer is cured so that the first resist layer does not dissolve in a resist solvent. Finally, a patterned second resist layer is formed on the cured first resist layer. The method of forming a dual-layer resist can be applied to mask ROM coding, hole formation and a dual damascene structure.
Abstract:
A rework process of patterned photo-resist layer is provided. First, a substrate is provided with a first DARC, a first primer and a first patterned photo-resist layer being sequentially formed thereon. Next, remove the first patterned photo-resist layer and the first primer from the first DARC. After that, form a second DARC on the first DARC; form a second primer on the second DARC. Last, form a second patterned photo-resist layer on the second primer.
Abstract:
A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.
Abstract translation:可以应用使用各向异性蚀刻的平面化方法来平坦化具有基板上的不平坦表面的绝缘层。 将H 2 SO 4,H 3 PO 4,HF和H 2 O混合以形成蚀刻溶液。 将衬底放置在蚀刻溶液中以使蚀刻溶液以流速通过绝缘层的表面以蚀刻绝缘层。 经过一段时间的蚀刻时间后,可获得具有更平坦表面的绝缘层。
Abstract:
A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the buried bit lines and between the gates, a plurality of word lines each disposed over a row of gates perpendicular to the buried bit lines, and a coding layer between the word lines and the gates.
Abstract:
A method of reducing charge loss for nonvolatile memory. First, a semiconductor substrate having a semiconductor device thereon is provided. Next, a dielectric layer is formed on the entire surface of the semiconductor substrate, and a thermal treatment is performed in an atmosphere containing a reactive gas, and the reactive gas reacts with free ions remaining on the semiconductor substrate from prior manufacturing processes. Finally, a metal layer is formed on the dielectric layer.
Abstract:
A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.