公开(公告)号：US06713388B2

公开(公告)日：2004-03-30

申请号：US10063199

申请日：2002-03-28

申请人： Uway Tseng ,  Ching-Yu Chang ,  Kent Kuohua Chang

发明人： Uway Tseng ,  Ching-Yu Chang ,  Kent Kuohua Chang

IPC分类号： H01L2131

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/76829 ,  H01L21/76831

摘要： A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.

摘要翻译： 存储器件形成在硅衬底上。 此后形成阻挡层以覆盖存储器件的堆叠栅极。 在阻挡层上形成吸气层，然后将吸气层平坦化至预定厚度。 然后在吸气层上形成第一阻挡层。 形成接触孔，以穿过第一阻挡层，吸气层和阻挡层，直到存储器件的表面。 之后，产生第二阻挡层以覆盖第一阻挡层和接触孔。 最后，第二阻挡层的部分被回蚀刻以在接触孔的侧壁上形成隔离隔离物。 其中，第一阻挡层和阻挡间隔物分别防止移动原子垂直扩散并横向扩散到存储器件中。

公开(公告)号：US06548425B2

公开(公告)日：2003-04-15

申请号：US09851570

申请日：2001-05-10

申请人： Kent Kuohua Chang ,  Uway Tseng

发明人： Kent Kuohua Chang ,  Uway Tseng

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/11568 ,  Y10S438/954

摘要： The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

公开(公告)号：US06413840B1

公开(公告)日：2002-07-02

申请号：US09821165

申请日：2001-03-28

申请人： Uway Tseng ,  Kent Kuohua Chang ,  Wen-Pin Lu

发明人： Uway Tseng ,  Kent Kuohua Chang ,  Wen-Pin Lu

IPC分类号： H01L21322

CPC分类号： H01L27/11526 ,  H01L23/26 ,  H01L27/105 ,  H01L27/11543 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile electrons with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.

摘要翻译： 提供了一种用于改进闪速存储器生产中的化学机械抛光工艺的吸气层的方法，以保护记忆元件免受烘烤，并通过用吸气层封闭移动电子来保持其可靠性。 此外，通过利用吸杂层，可以减小用于增加蚀刻余量的ILD的厚度，沉积裕度和氧化物的剩余余量。

公开(公告)号：US20070178664A1

公开(公告)日：2007-08-02

申请号：US11697751

申请日：2007-04-09

申请人： Uway Tseng ,  Ching-Yu Chang

发明人： Uway Tseng ,  Ching-Yu Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.

摘要翻译： 浅沟槽隔离结构具有在衬底中形成的沟槽，保形地形成在沟槽的侧壁和底部上的氧氮化硅层和基本上填充沟槽的高密度等离子体（HDP）氧化物层。

公开(公告)号：US20070020877A1

公开(公告)日：2007-01-25

申请号：US11186360

申请日：2005-07-21

申请人： Uway Tseng ,  Ching-Yu Chang

发明人： Uway Tseng ,  Ching-Yu Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.

摘要翻译： 浅沟槽隔离结构具有在衬底中形成的沟槽，保形地形成在沟槽的侧壁和底部上的氧氮化硅层和基本上填充沟槽的高密度等离子体（HDP）氧化物层。

公开(公告)号：US06746968B1

公开(公告)日：2004-06-08

申请号：US10364428

申请日：2003-02-12

申请人： Uway Tseng ,  Ching-Yu Chang ,  Hung-Yu Chiu ,  Wenpin Lu

发明人： Uway Tseng ,  Ching-Yu Chang ,  Hung-Yu Chiu ,  Wenpin Lu

IPC分类号： H01L2131

CPC分类号： H01L21/28273 ,  H01L21/02046 ,  H01L21/3105

摘要： A method of reducing charge loss for nonvolatile memory. First, a semiconductor substrate having a semiconductor device thereon is provided. Next, a dielectric layer is formed on the entire surface of the semiconductor substrate, and a thermal treatment is performed in an atmosphere containing a reactive gas, and the reactive gas reacts with free ions remaining on the semiconductor substrate from prior manufacturing processes. Finally, a metal layer is formed on the dielectric layer.

摘要翻译： 一种减少非易失性存储器的电荷损失的方法。 首先，提供其上具有半导体器件的半导体衬底。 接下来，在半导体衬底的整个表面上形成电介质层，并且在含有反应性气体的气氛中进行热处理，并且反应性气体与先前的制造工艺中留在半导体衬底上的游离离子进行反应。 最后，在电介质层上形成金属层。

公开(公告)号：US07387961B2

公开(公告)日：2008-06-17

申请号：US11048486

申请日：2005-01-31

申请人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

发明人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a second dielectric; forming a second dielectric insulator over the first dielectric insulator; forming a second opening in the second dielectric insulator overlying and communicating with the first opening; and, filling the first and second openings with a conductive material to electrically communicate with the conductive area.

公开(公告)号：US08344471B2

公开(公告)日：2013-01-01

申请号：US12511789

申请日：2009-07-29

申请人： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

发明人： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

IPC分类号： H01L31/00

CPC分类号： H01L27/14636 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/1464 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00

摘要： An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

摘要翻译： 集成电路包括具有焊盘区域和非接合焊盘区域的衬底。 在接合区域中的基板上形成相当大的通孔，称为大通孔。 大通孔在朝向基板的顶视图中具有第一尺寸。 集成电路还包括在非接合区域中形成在衬底上的多个通孔。 多个通孔各自在顶视图中具有第二尺寸，第二尺寸基本上小于第一尺寸。

公开(公告)号：US07884013B2

公开(公告)日：2011-02-08

申请号：US12154823

申请日：2008-05-27

申请人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

发明人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a second dielectric; forming a second dielectric insulator over the first dielectric insulator; forming a second opening in the second dielectric insulator overlying and communicating with the first opening; and, filling the first and second openings with a conductive material to electrically communicate with the conductive area.

摘要翻译： 具有改进的轮廓和减少的缺陷的双镶嵌结构及其形成方法，所述方法包括在导电区域上形成第一电介质; 在所述第一电介质上形成第一电介质绝缘体; 在所述第一介电绝缘体中形成第一开口; 用第二电介质衬里开口; 在所述第一绝缘绝缘体上形成第二电介质绝缘体; 在所述第二绝缘绝缘体中形成第二开口，所述第二开口覆盖并与所述第一开口连通; 并且用导电材料填充第一和第二开口以与导电区域电连通。

公开(公告)号：US20070102748A1

公开(公告)日：2007-05-10

申请号：US11269582

申请日：2005-11-09

申请人： Uway Tseng ,  Yao-Hui Huang

发明人： Uway Tseng ,  Yao-Hui Huang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate electrode. The gate electrode includes a substrate, a gate dielectric layer formed thereon, and a gate conductive layer comprising a stack of polysilicon grains formed on the gate dielectric layer, wherein the average size of the polysilicon grains decreases gradually in a direction away from the substrate. The invention also provides a metal oxide semiconductor (MOS) transistor including the gate and a method of fabricating the MOS transistor.

摘要翻译： 栅电极。 栅极电极包括基板，形成在其上的栅极电介质层和栅极导电层，栅极导电层包括形成在栅极介电层上的多晶硅晶粒堆叠，其中多晶硅晶粒的平均尺寸在远离衬底的方向上逐渐减小。 本发明还提供了包括栅极的金属氧化物半导体（MOS）晶体管和制造MOS晶体管的方法。