公开(公告)号：US20200152282A1

公开(公告)日：2020-05-14

申请号：US16189200

申请日：2018-11-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US20200090770A1

公开(公告)日：2020-03-19

申请号：US16143916

申请日：2018-09-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Disclosed herein is related to a system and a method of adjusting a programming pulse for programming memory cells. In one aspect, the system includes a controller that iteratively applies a programming pulse to the memory cells during programming loops. The programming pulse has progressively increasing magnitudes to program different subsets of the memory cells to corresponding target states. The controller determines that a programming loop to program a subset of the memory cells targeted to have a corresponding target state of the target states is performed. The controller counts a number of memory cells of the subset that have not reached the target state. The controller determines a magnitude for a programming pulse to be applied for a subsequent programming loop based on the counted number, and applies, during the subsequent programming loop, the programming pulse with the determined magnitude.

公开(公告)号：US10482985B2

公开(公告)日：2019-11-19

申请号：US16017996

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  H01L27/1157 ,  G11C11/56

Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.

公开(公告)号：US12243593B2

公开(公告)日：2025-03-04

申请号：US17685613

申请日：2022-03-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Ohwon Kwon ,  James Kai ,  Yuki Mizutani

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

公开(公告)号：US12148478B2

公开(公告)日：2024-11-19

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

公开(公告)号：US12142315B2

公开(公告)日：2024-11-12

申请号：US17825193

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Muhammad Masuduzzaman ,  Jiacen Guo

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.

公开(公告)号：US12045511B2

公开(公告)日：2024-07-23

申请号：US17898639

申请日：2022-08-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Wei Cao

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/0679

Abstract: The memory device has a plurality of memory blocks including a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry that is in communication with the plurality of memory blocks. The control circuitry is configured to receive a data write instruction. The control circuitry is further configured to program the memory cells of the memory blocks to an SLC format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry is configured to program the memory cells of at least some of the plurality of memory blocks from the SLC format to a TLC format.

公开(公告)号：US11990185B2

公开(公告)日：2024-05-21

申请号：US17888063

申请日：2022-08-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  YenLung Li ,  James Kai

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

公开(公告)号：US11972813B2

公开(公告)日：2024-04-30

申请号：US17556477

申请日：2021-12-20

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Swaroop Kaza ,  Laidong Wang

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3409

Abstract: A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at least substantially maintained. Additionally, systems and methods for adjusting sense time based on die-to-die variations are also disclosed.

公开(公告)号：US11955184B2

公开(公告)日：2024-04-09

申请号：US17740429

申请日：2022-05-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiaochen Zhu ,  Xiang Yang ,  Lito De La Rama ,  Yi Song ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/28 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.