公开(公告)号：US08878300B1

公开(公告)日：2014-11-04

申请号：US14030048

申请日：2013-09-18

Applicant: STMicroelectronics, Inc. ,  Globalfoundries Inc

Inventor： Qing Liu ,  Ruilong Xie

IPC: H01L21/70 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming a plurality of semiconductor fins on a substrate, forming a gate overlying the plurality of semiconductor fins, forming respective unmerged semiconductor regions on the semiconductor fins on opposing sides of the gate, and forming a dielectric layer overlying the unmerged semiconductor regions. The method may further include etching the dielectric layer to define contact recesses having recess bottoms exposing the unmerged semiconductor regions, forming a respective semiconductor layer on each of the exposed unmerged semiconductor regions to extend outwardly from adjacent portions of the recess bottom, and siliciding each of the semiconductor layers to define respective source and drain contacts extending outwardly from adjacent portions of the recess bottom.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成多个半导体鳍片，形成覆盖多个半导体鳍片的栅极，在栅极的相对侧上的半导体鳍片上形成相应的未掺杂半导体区域，并形成介电层 覆盖未加工的半导体区域。 该方法可以进一步包括蚀刻电介质层以限定具有暴露未掺杂半导体区域的凹陷底部的接触凹部，在每个暴露的非半导体区域上形成相应的半导体层，以从凹部底部的相邻部分向外延伸， 所述半导体层限定相应的源极和漏极触点，其从所述凹部底部的相邻部分向外延伸。

公开(公告)号：US08866204B2

公开(公告)日：2014-10-21

申请号：US13754614

申请日：2013-01-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Junli Wang

IPC: H01L21/82 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/82 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract translation: 描述了一种用于制造具有使翅片与基板绝缘的绝缘层的finFET器件的方法。 绝缘层可以防止否则将流过衬底中的体半导体材料的漏电流。 该结构可以由体半导体衬底开始制造，而不需要绝缘体上半导体衬底。 鳍结构可以通过外延生长形成，这可以提高器件中翅片高度的均匀性。

公开(公告)号：US20140291749A1

公开(公告)日：2014-10-02

申请号：US13852645

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prasanna KHARE ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US11133331B2

公开(公告)日：2021-09-28

申请号：US16180223

申请日：2018-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/092 ,  H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US10741698B2

公开(公告)日：2020-08-11

申请号：US16355398

申请日：2019-03-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/088

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10411140B2

公开(公告)日：2019-09-10

申请号：US15892028

申请日：2018-02-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: B81B7/02 ,  H01L29/84 ,  H01H59/00 ,  B82B3/00 ,  H01H1/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US10388772B2

公开(公告)日：2019-08-20

申请号：US16013095

申请日：2018-06-20

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/49

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

公开(公告)号：US10290636B2

公开(公告)日：2019-05-14

申请号：US14461769

申请日：2014-08-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L27/092 ,  H01L29/167 ,  H01L29/161 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/06

Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.

公开(公告)号：US10262905B2

公开(公告)日：2019-04-16

申请号：US14867797

申请日：2015-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L27/12 ,  H01L29/49 ,  H01L29/10

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

公开(公告)号：US10256304B2

公开(公告)日：2019-04-09

申请号：US15890880

申请日：2018-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/41 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20 ,  H01L29/417

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.