公开(公告)号：US09318342B2

公开(公告)日：2016-04-19

申请号：US14811987

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/311 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US09293587B2

公开(公告)日：2016-03-22

申请号：US13948374

申请日：2013-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（finFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 和嵌入式S / D的外延（epi）底部区域，外延底部区域计数器掺杂到嵌入式S / D的极性。 该器件还包括一组注入在epi底部区域下方的注入区域，其中该组注入区域可以是掺杂的，而epi底部区域未被掺杂。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

公开(公告)号：US20160064526A1

公开(公告)日：2016-03-03

申请号：US14471038

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/30604 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括在凹陷鳍结构上方的绝缘材料层中形成凹陷翅片结构和替换翅片空腔，在替换翅片腔中形成至少第一和第二独立的外延半导体材料层，其中每个 第一层和第二层具有不同浓度的锗，对第一层和第二层进行退火处理，以在翅片腔中形成基本上均匀的SiGe替换翅片，并且在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US09269628B1

公开(公告)日：2016-02-23

申请号：US14560557

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/762 ,  H01L21/02 ,  H01L21/00

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/0886

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of first and second fins that are made of different semiconductor materials that may be selectively etched relative to one another, forming a first insulating material between the plurality of first and second fins, forming an etch mask above the first and second fins that exposes a portion of at least one first fin and exposes a portion of at least one second fin, performing an etching process to remove the exposed portion of the at least one first fin selectively to the first insulating material and the exposed portion of the at least one second fin so as to thereby define at least one removed fin cavity in the first insulating material, removing the patterned etch mask, and forming a second insulating material in the at least one removed fin cavity.

Abstract translation: 本文公开的一种说明性方法包括形成多个第一和第二鳍片，其由可被相对于彼此选择性地蚀刻的不同半导体材料制成，在多个第一和第二鳍片之间形成第一绝缘材料， 在所述第一和第二鳍片上形成蚀刻掩模，所述蚀刻掩模暴露至少一个第一鳍片的一部分并暴露至少一个第二鳍片的一部分，执行蚀刻工艺以选择性地将所述至少一个第一鳍片的暴露部分去除 第一绝缘材料和所述至少一个第二翅片的暴露部分，从而在所述第一绝缘材料中限定至少一个移除的翅片空腔，去除所述图案化的蚀刻掩模，以及在所述至少一个移除的鳍中形成第二绝缘材料 腔。

公开(公告)号：US09245980B2

公开(公告)日：2016-01-26

申请号：US14242472

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。

公开(公告)号：US09184162B2

公开(公告)日：2015-11-10

申请号：US14615762

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US20150249152A1

公开(公告)日：2015-09-03

申请号：US14708405

申请日：2015-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/78603

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

公开(公告)号：US09117875B2

公开(公告)日：2015-08-25

申请号：US14155499

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US20150214365A1

公开(公告)日：2015-07-30

申请号：US14162948

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/161 ,  H01L27/088 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: An improved structure and methods of fabrication for finFET devices utilizing a cladding channel are disclosed. A staircase fin is formed where the fin comprises an upper portion of a first width and a lower portion of a second width, wherein the lower portion is wider than the upper portion. The narrower upper portion allows the cladding channel to be deposited and still have sufficient space for proper gate deposition, while the lower portion is wide to provide improved mechanical stability, which protects the fins during the subsequent processing steps.

Abstract translation: 公开了一种利用包层通道的finFET器件的改进的结构和制造方法。 形成阶梯翅片，其中翅片包括第一宽度的上部和第二宽度的下部，其中下部比上部宽。 较窄的上部允许沉积包层通道并且仍然具有足够的空间用于适当的栅极沉积，而下部较宽以提供改进的机械稳定性，其在随后的处理步骤期间保护翅片。

公开(公告)号：US20150200128A1

公开(公告)日：2015-07-16

申请号：US14155499

申请日：2014-01-15

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/762 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。