公开(公告)号：US20210035906A1

公开(公告)日：2021-02-04

申请号：US16875809

申请日：2020-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/288 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L23/528

Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.

公开(公告)号：US10784155B2

公开(公告)日：2020-09-22

申请号：US16657485

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US10727113B2

公开(公告)日：2020-07-28

申请号：US16704195

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ethan Hsiao ,  Chien Wen Lai ,  Chih-Ming Lai ,  Yi-Hsiung Lin ,  Cheng-Chi Chuang ,  Hsin-Ping Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/33 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/3105

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

公开(公告)号：US20200168458A1

公开(公告)日：2020-05-28

申请号：US16543814

申请日：2019-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chieh Liao ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Tai-I Yang ,  Hsin-Ping Chen

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

Abstract: A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.

公开(公告)号：US20200051853A1

公开(公告)日：2020-02-13

申请号：US16657485

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US20200006228A1

公开(公告)日：2020-01-02

申请号：US16380386

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US10483159B2

公开(公告)日：2019-11-19

申请号：US16010007

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US10290580B2

公开(公告)日：2019-05-14

申请号：US15819280

申请日：2017-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.

公开(公告)号：US10103102B2

公开(公告)日：2018-10-16

申请号：US15855795

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hua Chen ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Tien-Lu Lin ,  Tien-I Bao

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.

公开(公告)号：US09865539B2

公开(公告)日：2018-01-09

申请号：US15065310

申请日：2016-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hua Chen ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Tien-Lu Lin ,  Tien-I Bao

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion.