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公开(公告)号：US11411113B2
公开(公告)日：2022-08-09
申请号：US16927082
申请日：2020-07-13
发明人： Chin-Hsiang Lin , Tai-Chun Huang , Tien-I Bao
IPC分类号： H01L29/66 , H01L29/78 , H01L29/417 , H01L21/768 , H01L21/02 , H01L21/033 , H01L21/8234 , H01L23/528 , H01L21/8238
摘要： An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
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公开(公告)号：US20200343384A1
公开(公告)日：2020-10-29
申请号：US16927082
申请日：2020-07-13
发明人： Chin-Hsiang Lin , Tai-Chun Huang , Tien-I Bao
IPC分类号： H01L29/78 , H01L29/417 , H01L21/768 , H01L21/02 , H01L21/033 , H01L21/8234 , H01L23/528 , H01L29/66
摘要： An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
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公开(公告)号：US20200035809A1
公开(公告)日：2020-01-30
申请号：US16592955
申请日：2019-10-04
发明人： Wen-Kai Lin , Bo-Yu Lai , Li Chun Te , Kai-Hsuan Lee , Sai-Hooi Yeong , Tien-I Bao , Wei-Ken Lin
IPC分类号： H01L29/66 , H01L27/092 , H01L21/8238 , H01L29/08 , H01L29/78
摘要： Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
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公开(公告)号：US20200006059A1
公开(公告)日：2020-01-02
申请号：US16569791
申请日：2019-09-13
发明人： Chia Cheng Chou , Po-Cheng Shih , Li Chun Te , Tien-I Bao
IPC分类号： H01L21/02 , H01L21/311 , H01L21/768 , C23C16/30 , H01L23/532 , H01L23/535
摘要： Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.
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公开(公告)号：US10002826B2
公开(公告)日：2018-06-19
申请号：US14524228
申请日：2014-10-27
发明人： Tai-I Yang , Yu-Chieh Liao , Tien-Lu Lin , Tien-I Bao
IPC分类号： H01L29/76 , H01L23/522 , H01L23/485 , H01L29/417 , H01L29/78 , H01L21/768 , H01L23/532 , H01L29/66
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76879 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L23/53228 , H01L23/53257 , H01L29/41758 , H01L29/665 , H01L29/7833 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.
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公开(公告)号：US09806026B2
公开(公告)日：2017-10-31
申请号：US14708503
申请日：2015-05-11
发明人： Tsung-Min Huang , Chung-Ju Lee , Tien-I Bao
IPC分类号： H01L21/70 , H01L23/532 , H01L21/768 , H01L21/02 , H01L21/3105 , H01L23/528
CPC分类号： H01L23/5329 , H01L21/02126 , H01L21/02203 , H01L21/02321 , H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
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公开(公告)号：US09568677B2
公开(公告)日：2017-02-14
申请号：US13905404
申请日：2013-05-30
发明人： Chun-Hao Tseng , Ying-Hao Kuo , Hai-Ching Chen , Tien-I Bao
CPC分类号： G02B6/136 , G02B6/12004 , G02B6/43
摘要： Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.
摘要翻译： 提供形成波导结构的实施例。 波导结构包括基板，并且基板具有互连区域和波导区域。 波导结构还包括形成在衬底中的沟槽，并且沟槽具有倾斜的侧壁表面和基本平坦的底部。 波导结构还包括形成在基板上的底部包层，并且底部包层从互连区域延伸到波导区域，并且底部包层用作互连区域中的绝缘层。 波导结构还包括形成在倾斜侧壁表面上的底部包层上的金属层。
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公开(公告)号：US09373586B2
公开(公告)日：2016-06-21
申请号：US14218060
申请日：2014-03-18
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L23/48 , H01L23/538 , H01L23/528 , H01L23/532 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/32139 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L21/76892 , H01L23/5222 , H01L23/5226 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.
摘要翻译： 本公开涉及互连结构。 金属互连结构具有设置在半导体衬底上的金属体和从金属体延伸的突起。 阻挡层从金属体的第一侧壁延伸到金属体的相对的第二侧壁的突起上。 电介质材料层设置在与金属体和突起物抵接的位置上的半导体衬底之上。
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公开(公告)号：US20140225261A1
公开(公告)日：2014-08-14
申请号：US14258175
申请日：2014-04-22
发明人： Ming Han Lee , Hai-Ching Chen , Hsiang-Huan Lee , Tien-I Bao , Chi-Lin Teng
IPC分类号： H01L23/485 , H01L23/482
CPC分类号： H01L23/4827 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76852 , H01L21/76867 , H01L21/76885 , H01L21/76897 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.
摘要翻译： 本公开的一些实施例涉及用于连接半导体衬底的器件的互连结构。 所述互连结构包括在所述衬底上的电介质层和穿过所述电介质层的连续导电体。 连续导电体由下体区域和上体区域构成。 下体区域具有限定在连续导电体的相对的下侧壁之间的第一宽度，并且上体区域具有限定在连续导电体的相对的上侧壁之间的第二宽度。 第二宽度小于第一宽度。 阻挡层将连续导电体与电介质层分开。
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公开(公告)号：US20140197538A1
公开(公告)日：2014-07-17
申请号：US14218060
申请日：2014-03-18
发明人： Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L23/532 , H01L23/538
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/32139 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L21/76892 , H01L23/5222 , H01L23/5226 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.
摘要翻译： 本公开涉及互连结构。 金属互连结构具有设置在半导体衬底上的金属体和从金属体延伸的突起。 阻挡层从金属体的第一侧壁延伸到金属体的相对的第二侧壁的突起上。 电介质材料层设置在与金属体和突起物抵接的位置上的半导体衬底之上。
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