公开(公告)号：US11615982B2

公开(公告)日：2023-03-28

申请号：US17150552

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Meng-Han Chou

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/522

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

公开(公告)号：US20230062940A1

公开(公告)日：2023-03-02

申请号：US17461329

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer Dhanyakumar ,  Huicheng Chang ,  Keng-Chu Lin

IPC: H01L27/092 ,  H01L21/8238

Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

公开(公告)号：US20230034803A1

公开(公告)日：2023-02-02

申请号：US17650329

申请日：2022-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Yi-Syuan Siao ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

公开(公告)号：US20230010038A1

公开(公告)日：2023-01-12

申请号：US17472086

申请日：2021-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Chu ,  Han-De Chen ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/26 ,  H01J37/32

Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.

公开(公告)号：US20220415606A1

公开(公告)日：2022-12-29

申请号：US17458972

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chun-Liang Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01J37/20 ,  H01L21/66 ,  H01L21/265 ,  H01J37/317 ,  H01J37/22 ,  H01J37/304

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a positions of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

公开(公告)号：US11532485B2

公开(公告)日：2022-12-20

申请号：US17107558

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Tsan-Chun Wang ,  Liang-Yin Chen ,  Jing-Huei Huang ,  Lun-Kuang Tan ,  Huicheng Chang

IPC: H01L21/31 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

公开(公告)号：US20220367249A1

公开(公告)日：2022-11-17

申请号：US17377667

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

公开(公告)号：US20220359277A1

公开(公告)日：2022-11-10

申请号：US17815407

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Fu-Ming Huang ,  Kei-Wei Chen ,  Liang-Yin Chen ,  Tang-Kuei Chang ,  Yee-Chia Yeo ,  Wei-Wei Liang ,  Ji Cui

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L23/532

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20220328631A1

公开(公告)日：2022-10-13

申请号：US17344049

申请日：2021-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Wen-Yen Chen ,  Li-Ting Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

公开(公告)号：US20220310785A1

公开(公告)日：2022-09-29

申请号：US17566316

申请日：2021-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Wu ,  Chia-Ling Chung ,  Su-Hao Liu ,  Liang-Yin Chen ,  Shun-Wu Lin ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/425

Abstract: A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.