公开(公告)号：US07568193B2

公开(公告)日：2009-07-28

申请号：US10767480

申请日：2004-01-28

Applicant: Norman Rubin ,  Myron King

Inventor： Norman Rubin ,  Myron King

IPC: G06F9/45

CPC classification number: G06F8/4435

Abstract: A method and apparatus for SSA dead code elimination includes examining a first instruction off a worklist, wherein the first instruction includes previous link and a write mask and the first instruction is an SSA instruction. The method and apparatus further includes examining at least one second instruction of the machine code, wherein the at least one second instructions are sources of the first instruction and the at least one second instructions are SSA instruction. In the method and apparatus, each of the at least one second instructions include a previous link and a write mask. The method and apparatus further includes determining if any components within a particular field of the at least one second instruction are live. If none of the components are live, the method and apparatus provides for deleting the second instruction from the machine code as it is determined that this instruction is extraneous, dead code.

Abstract translation: 一种用于SSA死代码消除的方法和装置，包括检查工作列表之外的第一指令，其中第一指令包括先前链接和写掩码，第一指令是SSA指令。 所述方法和装置还包括检查所述机器码的至少一个第二指令，其中所述至少一个第二指令是所述第一指令的源，并且所述至少一个第二指令是SSA指令。 在该方法和装置中，至少一个第二指令中的每一个包括先前的链接和写入掩码。 所述方法和装置还包括确定所述至少一个第二指令的特定字段内的任何组件是否是活的。 如果没有一个组件是实时的，则该方法和装置提供从机器代码中删除第二条指令，因为确定该指令是无关紧要的死码。

公开(公告)号：US20090091569A1

公开(公告)日：2009-04-09

申请号：US11868814

申请日：2007-10-08

Applicant: Petri O. Nordlund ,  Mika H. Tuomi

Inventor： Petri O. Nordlund ,  Mika H. Tuomi

IPC: G06T15/40

CPC classification number: G06T15/005 ,  G06T11/40 ,  G06T15/40

Abstract: An apparatus for rendering an image includes a command binning module. The command binning module generates binned image information by classifying command information into bins that each correspond to a display tile of an image to be rendered. The command binning module generates image depth information for each display tile based on the binned command information.

Abstract translation: 用于渲染图像的装置包括命令分档模块。 命令合并模块通过将命令信息分类为每个对应于要呈现的图像的显示图块的分块来生成分箱图像信息。 命令合并模块基于分箱命令信息生成每个显示瓦片的图像深度信息。

公开(公告)号：US20090086865A1

公开(公告)日：2009-04-02

申请号：US11864004

申请日：2007-09-28

Applicant: Oleg Drapkin ,  Grigori Temkine

Inventor： Oleg Drapkin ,  Grigori Temkine

IPC: H04B1/10

CPC classification number: H04L25/085

Abstract: A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.

Abstract translation: 差分信号比较器包括输入电路，其可操作以提供与差分输入信号电平的绝对差相关联的绝对输入电流差值，以及参考电路，用于提供与绝对差相关联的绝对参考电流差值 的参考信号电平。 绝对输入电流差值与绝对参考电流差值的当前比较表明输入差分信号是否大于参考噪声电平，应进行处理，或输入差分信号小于参考噪声电平，不应为 处理。

公开(公告)号：US07487378B2

公开(公告)日：2009-02-03

申请号：US11231078

申请日：2005-09-19

Applicant: Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

Inventor： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC classification number: H04L7/02 ,  H04L7/0025 ,  H04L7/0091

Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract translation: 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

公开(公告)号：US07440677B2

公开(公告)日：2008-10-21

申请号：US11019246

申请日：2004-12-23

Applicant: David A. Strasser

Inventor： David A. Strasser

IPC: H04N7/08

CPC classification number: H04N5/913 ,  H04N2005/91328

Abstract: To detect at least one of a copy protection indicator and a redistribution control indicator in an analog video signal, the video format of the analog video signal is determined, e.g., by detecting the horizontal frequency and vertical frequency of the signal. Based at least on the determined video format, a region of the analog video signal that may contain the indicator is identified. The region may for example be one or more video lines in a vertical blanking interval. The region is examined until the indicator is detected. The indicator is confirmed, e.g., by re-detecting one or more occurrences of the same indicator value(s) later in the video signal. Once confirmed, the indicated copy protection and/or redistribution control may be effected by limiting either or both of copying and redistribution of the analog video signal. The indicator may for example be Copy Generation Management System Analog plus Redistribution Control (CGMS-A+RC) information.

Abstract translation: 为了检测模拟视频信号中的复制保护指示符和再分配控制指示符中的至少一个，例如通过检测信号的水平频率和垂直频率来确定模拟视频信号的视频格式。 至少基于所确定的视频格式，识别可以包含指示符的模拟视频信号的区域。 该区域可以例如是垂直消隐间隔中的一个或多个视频行。 检查该区域直到检测到指示符。 例如，通过重新检测视频信号中稍后出现的相同指示符值的一个或多个出现来确认指示符。 一旦被确认，所指示的复制保护和/或再分配控制可以通过限制模拟视频信号的复制和重新分配中的一个或两者来实现。 指示器可以例如是复制生成管理系统模拟加再分配控制（CGMS-A + RC）信息。

公开(公告)号：US07434024B2

公开(公告)日：2008-10-07

申请号：US10929992

申请日：2004-08-30

Applicant: Richard J. Selvaggi ,  Larry A. Pearlstein

Inventor： Richard J. Selvaggi ,  Larry A. Pearlstein

IPC: G06F9/26 ,  G06F9/34 ,  G06F12/02

CPC classification number: G06F9/345 ,  G06F9/30101 ,  G06F9/3555

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

Abstract translation: 公开了一种用于灵活计算有效操作数源和目的地存储器地址的单指令多数据（SIMD）处理器，包括多个寻址寄存器组。 两个或多个地址生成器使用寄存器集计算有效地址。 每个寄存器组包括一个指针寄存器和一个比例寄存器。 地址生成器从所选择的寄存器组的指针寄存器和比例寄存器形成有效地址; 和一个偏移。 例如，有效存储器地址可以通过将比例值乘以偏移值并将指针与刻度值相乘而乘以偏移值来形成。

公开(公告)号：US20080197477A1

公开(公告)日：2008-08-21

申请号：US12110798

申请日：2008-04-28

Applicant: Neil R. McLellan ,  Vincent K. Chan ,  Roden R. Topacio

Inventor： Neil R. McLellan ,  Vincent K. Chan ,  Roden R. Topacio

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages.

Abstract translation: 本公开涉及一种改进的集成电路封装，其具有邻近衬底上的封装集成芯片定位的密封剂保留结构。 该结构允许在封装的集成芯片下放置和保留更大量的密封剂渗入。 放置在基板上的保持壁交替地用作能够保持机械性能以与更理想的较薄基板一起使用的基板加强件。 在一个实施例中，使用集成电路封装的加强层中的开口和凹槽容纳无源电子部件，以在使用更薄的衬底时保持机械特性。 使用保留壁或加强件允许使用条带，矩阵或阵列技术来制造这些集成电路封装，其中具有多个集成电路封装的较大的板在工业上被制造然后切割成各个单元。 在昂贵的基底层上使用加强层的保持壁允许使用围绕条带的一次性边缘，包括分度孔或其它保持机构。 还可以想到的是制造由多个集成电路封装组成的紧凑型条，矩阵或阵列的方法，其中不需要浪费或额外的切割来产生单独的集成电路封装。

公开(公告)号：USD574778S1

公开(公告)日：2008-08-12

申请号：US29237320

申请日：2005-08-31

Applicant: Colin Szeto ,  Blair A. Birmingham ,  John R. Shaw ,  John Giordano ,  Miro Glisch

Designer： Colin Szeto ,  Blair A. Birmingham ,  John R. Shaw ,  John Giordano ,  Miro Glisch

公开(公告)号：US20080059824A1

公开(公告)日：2008-03-06

申请号：US11469153

申请日：2006-08-31

Applicant: Omid Rowhani ,  Vincent Ross

Inventor： Omid Rowhani ,  Vincent Ross

IPC: H02J1/00 ,  G06F1/00

CPC classification number: H03K17/167 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/461

Abstract: A method and apparatus for selectively charging a secondary voltage rail includes selectively and partially charging a secondary voltage rail using at least one soft start power gate switch and using an initial power control indicator. The partially charged secondary voltage rail is selectively charged, using at least one main power gate switch, based on the initial power control indicator and a detected voltage on the secondary voltage rail. When the initial power control indicator is in a state representative of an initial power up command and when the detected voltage is greater than or equal to a predetermined voltage level, at least one main power gate switch is closed thereby charging the secondary voltage rail.

Abstract translation: 用于选择性地对次级电压轨进行充电的方法和装置包括使用至少一个软启动功率门开关并使用初始功率控制指示器来选择性地和部分地对次级电压轨充电。 使用至少一个主电源栅极开关，基于初始功率控制指示器和次级电压轨上的检测电压，选择性地对部分充电的次级电压轨进行充电。 当初始功率控制指示器处于表示初始上电命令的状态下，并且当检测到的电压大于或等于预定电压电平时，关闭至少一个主电源门开关，从而对次级电压轨充电。

公开(公告)号：US20080057918A1

公开(公告)日：2008-03-06

申请号：US11468982

申请日：2006-08-31

Applicant: Robert Abrant ,  Mark Bapst ,  Satyajit Patne

Inventor： Robert Abrant ,  Mark Bapst ,  Satyajit Patne

IPC: H04M3/42

CPC classification number: H04H20/26 ,  H04H20/42 ,  H04H60/33 ,  H04W52/0274 ,  H04W52/0287 ,  Y02D70/168

Abstract: A current mobile multimedia signal time slice is captured using a mobile MM receiver in response to a current mobile multimedia stream-identifying command input. The current mobile multimedia signal time slice contains at least one portion of a currently selected mobile multimedia stream. At least one anticipated mobile multimedia time slice is selectively captured. The at least one anticipated mobile multimedia time slice contains at least one portion of a corresponding anticipated mobile multimedia stream.

Abstract translation: 响应于当前的移动多媒体流标识命令输入，使用移动MM接收机捕获当前移动多媒体信号时间片。 当前移动多媒体信号时间片包含当前选择的移动多媒体流的至少一部分。 选择性地捕获至少一个预期的移动多媒体时间片。 所述至少一个预期的移动多媒体时间片段包含对应的预期移动多媒体流的至少一部分。