Processors supporting atomic writes to multiword memory locations and methods

    公开(公告)号:US10649773B2

    公开(公告)日:2020-05-12

    申请号:US15092915

    申请日:2016-04-07

    申请人: MIPS Tech, LLC

    摘要: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

    Vehicular cognitive data collection using multiple devices

    公开(公告)号:US10592757B2

    公开(公告)日:2020-03-17

    申请号:US15886275

    申请日:2018-02-01

    申请人: Affectiva, Inc.

    摘要: Vehicle cognitive data is collected using multiple devices. A user interacts with various pieces of technology to perform numerous tasks and activities. Reactions can be observed and cognitive states inferred from reactions to the tasks and activities. A first computing device within a vehicle obtains cognitive state data which is collected on an occupant of the vehicle from multiple sources, wherein the multiple sources include at least two sources of facial image data. A second computing device generates analysis of the cognitive state data which is collected from the multiple sources. A third computing device renders an output which is based on the analysis of the cognitive state data. The cognitive state data from multiple sources is tagged. The cognitive state data from the multiple sources is aggregated. The cognitive state data is interpolated when collection is intermittent. The cognitive state analysis is interpolated when the cognitive state data is intermittent.

    Audio analysis learning with video data

    公开(公告)号:US10573313B2

    公开(公告)日:2020-02-25

    申请号:US16272054

    申请日:2019-02-11

    申请人: Affectiva, Inc.

    摘要: Audio analysis learning is performed using video data. Video data is obtained, on a first computing device, wherein the video data includes images of one or more people. Audio data is obtained, on a second computing device, which corresponds to the video data. A face within the video data is identified. A first voice, from the audio data, is associated with the face within the video data. The face within the video data is analyzed for cognitive content. Audio features corresponding to the cognitive content of the video data are extracted. The audio data is segmented to correspond to an analyzed cognitive state. An audio classifier is learned, on a third computing device, based on the analyzing of the face within the video data. Further audio data is analyzed using the audio classifier.

    Decentralized competitive arbitration using digital ledgering

    公开(公告)号:US10572872B2

    公开(公告)日:2020-02-25

    申请号:US15861948

    申请日:2018-01-04

    摘要: Disclosed techniques enable arbitration of electronic competitions using digital ledgering. A digital competition arbitration platform is based on secure, trusted digital ledgering techniques. Users who seek to compete in digital games and eSports subscribe to the arbitration platform. A competition between users employs a digital contract. The contract is executed using a digital ledger token. The outcome of the competition between players is verified based on input from both the competitors and randomly selected witnesses. When a dispute occurs between the players, a juror pool reviews evidence and witness results. Payouts are made based on the digital contract and the adjudged competition result. Compensation is provided to jurors and witnesses.

    Communication between dataflow processing units and memories

    公开(公告)号:US10564929B2

    公开(公告)日:2020-02-18

    申请号:US15665631

    申请日:2017-08-01

    摘要: A combination of memory units and dataflow processing units is disclosed for computation. A first memory unit is interposed between a first dataflow processing unit and a second dataflow processing unit. Operations for a dataflow graph are allocated across the first dataflow processing unit and the second dataflow processing unit. The first memory unit passes data between the first dataflow processing unit and the second dataflow processing unit to execute the dataflow graph. The first memory unit is a high bandwidth, shared memory device including a hybrid memory cube. The first dataflow processing unit and second dataflow processing unit include a plurality of circular buffers containing instructions for controlling data transfer between the first dataflow processing unit and second dataflow processing unit. Additional dataflow processing units and additional memory units are included for additional functionality and efficiency.

    Musical attribution in a two-dimensional digital representation

    公开(公告)号:US10553188B2

    公开(公告)日:2020-02-04

    申请号:US15854006

    申请日:2017-12-26

    申请人: CharmPI, LLC

    发明人: Wu-Hsi Li

    IPC分类号: A63H5/00 G04B13/00 G10H1/00

    摘要: Musical attribution is performed in a two-dimensional (2D) digital representation. A piece of music representing a musical score is inputted. An abstracted representation of blanks of the score, called a digital audio canvas, is produced. Interactive, dynamic attribution is performed by a user to bring to life the musical score of abstracted blanks. Instrumentation selection, relative volume, scale selection, and score tempo are all musical attributes that are conveyed to the score of abstracted blanks. The score of the digital audio canvas is played back using the attributed blanks. The playback of the score is enabled by selecting appropriate abstracted blanks. The appropriate abstracted blanks are included among other blanks for increased educational and enjoyment value. The modified score is converted back into the format of the original inputted piece of music.

    Data storage system with configurable prefetch buffers

    公开(公告)号:US10459842B1

    公开(公告)日:2019-10-29

    申请号:US15904322

    申请日:2018-02-24

    摘要: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

    Reconfigurable processor fabric implementation using satisfiability analysis

    公开(公告)号:US10452452B2

    公开(公告)日:2019-10-22

    申请号:US15953896

    申请日:2018-04-16

    IPC分类号: G06F9/50 G06F15/78

    摘要: Disclosed techniques utilize a satisfiability solver for allocation and/or configuration of resources in a reconfigurable fabric of processing elements. A dataflow graph is an input provided to a toolchain that includes a satisfiability solver. The satisfiability solver operates on subsets of interconnected nodes within a dataflow graph to derive a solution. The solution is trimmed by removing artifacts and unnecessary parts. The solutions of subsets are then used as an input to additional subsets of nodes within the dataflow graph in an iterative process to derive a complete solution. The satisfiability solver technique uses adaptive windowing in both the time dimension and the spatial dimensions of the dataflow graph. Processing elements and routing elements within the reconfigurable fabric are configured based on the complete solution. Data computation is performed based on the dataflow graph using the processing elements and the routing resources.