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11.发明授权Method for integrating imperfect semiconductor memory devices in data processing apparatus 有权在数据处理装置中集成不完美的半导体存储器件的方法公开(公告)号：US06762965B2
公开(公告)日：2004-07-13
申请号：US10254694
申请日：2002-09-25
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.
摘要翻译： 一种用于将具有功能和缺陷存储器单元的不完美半导体存储器件集成到数据处理装置中的方法。 缺陷存储单元被分配缺陷地址或缺陷地址范围。 在执行数据处理装置的存储器访问之前，将存储器访问的地址与缺陷地址或缺陷地址范围进行比较，并且在对应的情况下被重新编码。
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公开(公告)号：US06590824B2
公开(公告)日：2003-07-08
申请号：US10112521
申请日：2002-03-28
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/062 , G11C7/14 , G11C11/4091 , G11C11/4099
摘要： A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with the memory banks for storing an address of an open, activated word line. In the event of an external refresh command, a control device causes, after the refresh operation, the state of the memory banks to be reestablished, in particular, the word line whose address was stored in the register to be reactivated. Such a purely on-chip measure increases the operating speed of the memory.
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公开(公告)号：US06876217B2
公开(公告)日：2005-04-05
申请号：US10272344
申请日：2002-10-15
CPC分类号： G11C29/40 , G11C2029/2602
摘要： To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines—used in the process—of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.
摘要翻译： 为了能够以特别快速且可靠的方式测试多个相同的半导体电路器件，测试方法包括并行并且基本上同时地在用于该过程的多个半导体电路器件和驱动器线路上执行测试 用于半导体电路装置的测试装置，同时并共同地用于所有半导体电路装置。 在这种情况下，从压缩形式的多个输入/输出通道读取测试结果。 此外，作为替代或补充，待测试的半导体电路器件被布置并连接到至少一个堆叠中。
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14.发明授权公开(公告)号：US06806121B2
公开(公告)日：2004-10-19
申请号：US10285090
申请日：2002-10-31
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1′; B1″), which is composed of a plurality of interconnect sections (A11-A16; A11′-A16′; A11″-A14″) lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2′; B2″), which runs adjacent to the first interconnect (B1; B1′; B1″) and which is composed of a plurality of interconnect sections (A21-A25; A21′-A25′; A21″-A23″) lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1′; B1″; B2; B2′; B2″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12′, A14′, A16′; A12″, A14″) of the first interconnect (B1; B1′; B1″) which lie in the first interconnect plane (M0) run at least in sections beside the interconnect sections (A22, A24; A22′; A24′; A21″, A23″) of the second interconnect (B2; B2′; B2″) which lie in the second interconnection plane (M1), and that the interconnect sections (A11, A13, A15; A11′, A13′, A15′; A11″, A13″) of the first interconnect (B1; B1′; B1″) which lie in the second interconnect plane (M1) run at least in sections beside the interconnect sections (A21, A23, A25; A21′, A23′, A25′; A22″) of the second interconnect (B2; B2′; B2″) which lie in the first interconnect plane (M0). The invention also provides a corresponding fabrication method.
摘要翻译： 本发明涉及具有第一互连（B1; B1'; B1“）的集成电路（1）的互连结构，其由多个互连部分（A11-A16; A11'-A16'）组成; A11“-A14”），位于第一和第二互连平面（M0，M1）中; 和与第一互连（B1; B1'; B1“）相邻的第二互连（B2; B2'; B2”），它们由多个互连部分（A21-A25; A21'- A25“; A21”-A23“），位于第一和第二互连平面（M0，M1）中; 第一和第二互连（B1; B1'; B1“; B2; B2'; B2”）在纵向方向上彼此偏移，使得互连部分（A12，A14，A16; 位于第一互连平面（M0）中的第一互连（B1; B1'; B1“）的A12'，A14'，A16'; A12”，A14“）至少在互连部分旁边 位于第二互连平面（M1）中的第二互连（B2; B2'; B2“）的位置（A22，A24; A22'; A24'; A21”，A23“）， A11，A13，A
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公开(公告)号：US06738304B2
公开(公告)日：2004-05-18
申请号：US10283992
申请日：2002-10-30
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.
摘要翻译： 根据一个实施例，提供动态存储器。 动态存储器可以包括具有以行和列排列的多个存储器单元的存储器矩阵。 在每种情况下，可以连接多行字线中的一行中的存储单元。 列中的存储单元可以在每种情况下连接多个位线中的一个。 动态存储器还可以包括用于经由多个位线从存储器单元读取数据的读出放大器。 此外，动态存储器可以包括行地址解码器和用于以取决于存储器 - 外部地址信号的方式产生存储器内部地址的列地址解码器。 动态存储器还可以包括用于循环产生刷新地址以执行对存储器单元进行刷新操作的序列控制装置。
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公开(公告)号：US06635947B2
公开(公告)日：2003-10-21
申请号：US09934979
申请日：2001-08-21
申请人： Alexander Benedix , Georg Braun , Helmut Fischer , Bernd Klehn , Sebastian Kuhne
发明人： Alexander Benedix , Georg Braun , Helmut Fischer , Bernd Klehn , Sebastian Kuhne
IPC分类号： H01L2900
摘要： A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.
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公开(公告)号：US06556496B2
公开(公告)日：2003-04-29
申请号：US09941902
申请日：2001-08-29
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.
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公开(公告)号：US06483166B2
公开(公告)日：2002-11-19
申请号：US09867486
申请日：2001-05-30
申请人： Alexander Benedix
发明人： Alexander Benedix
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2224/48091 , H01L2924/00014
摘要： The semiconductor configuration has a packing material that is permeable to radiation energy in a given wavelength band. One or more fuses that adjoin the packing material absorb the energy in the given wavelength band. The fuses are formed of AIIIBV semiconductor material, of titanium silicide, germanium, PbS, InSb, or of SiGe.
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公开(公告)号：US06820197B2
公开(公告)日：2004-11-16
申请号：US10000690
申请日：2001-11-15
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： G06F15177
CPC分类号： G06F9/4411 , G06F15/177
摘要： The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the configuration registers to a non-volatile memory so that a serial transmission of data from the non-volatile memory to the configuration registers is made possible, for example when the system is booted up. The system already functions even if complex bus systems, such as extensively parallel high-speed buses, for example, are not yet available in a configuration process of the system. The system can be used in all data processing systems, in particular in mobile applications.
摘要翻译： 数据处理系统具有可配置的组件，每个组件具有用于存储配置数据的配置寄存器。 串行总线将配置寄存器耦合到非易失性存储器，使得可以例如当系统启动时将数据从非易失性存储器串行传输到配置寄存器。 即使在系统的配置过程中，诸如广泛并行的高速总线之类的复杂总线系统尚不可用，该系统也已经起作用。 该系统可用于所有数据处理系统，特别是在移动应用中。
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20.发明授权公开(公告)号：US06738309B2
公开(公告)日：2004-05-18
申请号：US10154597
申请日：2002-05-23
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/22 , G11C7/222
摘要： A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.
摘要翻译： 描述了具有时钟输入，信号输入，数据输出，测量装置，控制电路和等待时间的半导体存储器。 在信号输入的激活和在数据输出端要读取的数据的可用性之间经过了延迟。 时钟信号被馈送到时钟输入。 基于时钟信号，测量装置确定延迟的值，并且控制电路以半导体存储器的操作的确定值配置半导体存储器。
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