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1.发明授权公开(公告)号：US06738309B2
公开(公告)日：2004-05-18
申请号：US10154597
申请日：2002-05-23
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/22 , G11C7/222
摘要： A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.
摘要翻译： 描述了具有时钟输入，信号输入，数据输出，测量装置，控制电路和等待时间的半导体存储器。 在信号输入的激活和在数据输出端要读取的数据的可用性之间经过了延迟。 时钟信号被馈送到时钟输入。 基于时钟信号，测量装置确定延迟的值，并且控制电路以半导体存储器的操作的确定值配置半导体存储器。
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公开(公告)号：US06665228B2
公开(公告)日：2003-12-16
申请号：US10166962
申请日：2002-06-11
IPC分类号： G11C800
CPC分类号： G11C11/4087 , G11C8/14
摘要： An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.
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公开(公告)号：US06635947B2
公开(公告)日：2003-10-21
申请号：US09934979
申请日：2001-08-21
申请人： Alexander Benedix , Georg Braun , Helmut Fischer , Bernd Klehn , Sebastian Kuhne
发明人： Alexander Benedix , Georg Braun , Helmut Fischer , Bernd Klehn , Sebastian Kuhne
IPC分类号： H01L2900
摘要： A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.
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公开(公告)号：US07065687B2
公开(公告)日：2006-06-20
申请号：US10253465
申请日：2002-09-24
摘要： A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.
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公开(公告)号：US06522588B2
公开(公告)日：2003-02-18
申请号：US09932893
申请日：2001-08-20
申请人： Alexander Benedix
发明人： Alexander Benedix
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A description is given of a method and a device for outputting data via a buffer memory. In which the data, which are intended to be output first from the buffer memory are selected. The selected data are written either to a predetermined area of the buffer memory and/or to the buffer memory temporally before the rest of the data and output.
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公开(公告)号：US06820197B2
公开(公告)日：2004-11-16
申请号：US10000690
申请日：2001-11-15
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： G06F15177
CPC分类号： G06F9/4411 , G06F15/177
摘要： The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the configuration registers to a non-volatile memory so that a serial transmission of data from the non-volatile memory to the configuration registers is made possible, for example when the system is booted up. The system already functions even if complex bus systems, such as extensively parallel high-speed buses, for example, are not yet available in a configuration process of the system. The system can be used in all data processing systems, in particular in mobile applications.
摘要翻译： 数据处理系统具有可配置的组件，每个组件具有用于存储配置数据的配置寄存器。 串行总线将配置寄存器耦合到非易失性存储器，使得可以例如当系统启动时将数据从非易失性存储器串行传输到配置寄存器。 即使在系统的配置过程中，诸如广泛并行的高速总线之类的复杂总线系统尚不可用，该系统也已经起作用。 该系统可用于所有数据处理系统，特别是在移动应用中。
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7.发明授权Testing a data store using an external test unit for generating test sequence and receiving compressed test results 失效使用外部测试单元测试数据存储，以生成测试序列并接收压缩测试结果公开(公告)号：US07428662B2
公开(公告)日：2008-09-23
申请号：US10478403
申请日：2002-05-15
IPC分类号： G06F11/00 , G06F11/277
摘要： Disclosed is a test method for testing a data store having an integrated test data compression circuit where the data store has a memory cell array with a multiplicity of addressable memory cells, read/write amplifiers for reading and writing data to the memory cell via an internal data bus in the data store and a test data compression circuit which compresses test data sequences, which are each read serially from the memory cell array, with stored reference test data sequences in order to produce a respective indicator data item which indicates whether at least one data error has occurred in the test data sequence which has been read.
摘要翻译： 公开了一种用于测试具有集成测试数据压缩电路的数据存储器的测试方法，其中数据存储器具有具有多个可寻址存储器单元的存储单元阵列，用于经由内部存储器单元向存储器单元读取和写入数据的读/写放大器 数据存储器中的数据总线和压缩从存储单元阵列中串行读取的测试数据序列的测试数据压缩电路与存储的参考测试数据序列一起，以产生相应的指示符数据项，该指示符数据项指示是否至少一个 已经读取的测试数据序列中发生了数据错误。
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公开(公告)号：US07127553B2
公开(公告)日：2006-10-24
申请号：US10717337
申请日：2003-11-19
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： H01L27/108
CPC分类号： G06F11/3409
摘要： A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.
摘要翻译： 用于执行数据处理过程的配置具有由操作系统使用用于执行系统进程的访问策略来访问的操作系统和各种系统资源。 当有不同的应用程序时，使用与系统资源不同的访问策略。 还提供了一种用于确定对系统资源的最佳访问策略的方法。
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9.发明授权Method for testing a device and a test configuration including a device with a test memory 有权用于测试设备的方法和包括具有测试存储器的设备的测试配置公开(公告)号：US06895538B2
公开(公告)日：2005-05-17
申请号：US09907694
申请日：2001-07-18
IPC分类号： G11C29/44 , H01L23/544 , G11C29/00
CPC分类号： H01L23/544 , G11C29/44 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.
摘要翻译： 包括用于测试设备的测试配置和测试设备的方法，其中在设备测试期间确定测试结果被存储在设备中的存储器中。 以这种方式，测试结果与设备连接，随时可用于以后的评估。
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10.发明授权Method for storing data in a memory device with the possibility of access to redundant memory cells 有权将数据存储在具有访问冗余存储单元的可能性的存储器件中的方法公开(公告)号：US06819606B2
公开(公告)日：2004-11-16
申请号：US10339031
申请日：2003-01-09
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step for providing redundant memory cells in the memory device. The method can also include a step for localizing defective cells. Further, the method can include a step of accessing the redundant memory cells by means of a predeterminable access mode. The method can also include a step of bypassing defective memory cells of the memory device in a manner dependent on the predeterminable access mode during operation of the memory device for accessing redundant memory cells and for replacement by redundant memory cells. Further, the method can include a step for providing redundant memory cells for storing additional information describing a defect correction.
摘要翻译： 提供了一种用于将数据存储在具有布置在存储单元行和存储单元列中的存储单元的存储器件中的方法。 该方法可以包括在存储器件中提供冗余存储器单元的步骤。 该方法还可以包括用于定位缺陷单元的步骤。 此外，该方法可以包括通过可预定访问模式访问冗余存储器单元的步骤。 该方法还可以包括在存储器设备的操作期间以取决于可预定访问模式的方式绕过存储器件的有缺陷的存储单元的步骤，用于访问冗余存储器单元并由冗余存储器单元替换。 此外，该方法可以包括用于提供用于存储描述缺陷校正的附加信息的冗余存储器单元的步骤。
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