公开(公告)号：US20060205140A1

公开(公告)日：2006-09-14

申请号：US11077074

申请日：2005-03-10

申请人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

发明人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/40 ,  Y10S438/952

摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

摘要翻译： 公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。 电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。 在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。 薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

公开(公告)号：US20060194401A1

公开(公告)日：2006-08-31

申请号：US11068117

申请日：2005-02-28

申请人： Binghua Hu ,  Sameer Pendharkar ,  Bill Wofford ,  Joseph Ramirez

发明人： Binghua Hu ,  Sameer Pendharkar ,  Bill Wofford ,  Joseph Ramirez

IPC分类号： H01L21/331 ,  H01L21/76

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/2652 ,  H01L21/823493 ,  H01L21/8249 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

摘要翻译： 本发明提供一种具有对准特征的半导体器件的制造方法。 除了其他步骤之外，制造半导体器件的方法可以包括将n型掺杂剂注入衬底中，从而在衬底中形成注入区域和未被注入的区域。 该方法可以进一步包括使用湿式氧化法，湿式氧化法和n型掺杂剂使注入区域与未被注入的区域的氧化比例为2:1或更大，然后除去氧化部分 从而在植入区域附近留下对准特征。

公开(公告)号：US08399924B2

公开(公告)日：2013-03-19

申请号：US13160759

申请日：2011-06-15

申请人： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

发明人： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

公开(公告)号：US20120164814A1

公开(公告)日：2012-06-28

申请号：US13409689

申请日：2012-03-01

申请人： Sameer P. PENDHARKAR ,  Binghua HU

发明人： Sameer P. PENDHARKAR ,  Binghua HU

IPC分类号： H01L21/76

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/66136

摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

摘要翻译： 公开了一种高压二极管，其中n型阴极由未接触的重掺杂n型环包围以将注入的孔反射回阴极区域进行复合或收集。 重掺杂n型环中的掺杂剂密度优选为阴极中掺杂剂密度的100至10,000倍。 重掺杂的n型区通常连接到阴极下方的n型掩埋层。 重掺杂的n型环优选地从阴极触点定位至少一个孔扩散长度。 所公开的高电压二极管可以集成到集成电路中，而不需要添加工艺步骤。

公开(公告)号：US20110309440A1

公开(公告)日：2011-12-22

申请号：US13160759

申请日：2011-06-15

申请人： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

发明人： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

摘要翻译： 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

公开(公告)号：US07829430B2

公开(公告)日：2010-11-09

申请号：US11968085

申请日：2007-12-31

申请人： Sameer Pendharker ,  Binghua Hu

发明人： Sameer Pendharker ,  Binghua Hu

IPC分类号： H01L21/762 ,  H01L21/3213

CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207

摘要： Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained.

摘要翻译： 提供了设备和方法以在衬底上的隔离区域中制造虚设的护城河。 目前，在硅化处理之后，假山羊容易失去阻抗。 在高压设备中，硅化虚拟护城河降低了活性区域之间的击穿电压，特别是当虚拟护套重叠或接近结点时。 本发明的装置和方法公开了覆盖有氧化物层的虚拟护城河。 在硅化过程中，虚拟护城河和其他指定的隔离区域保持非硅化。 因此，保持高且稳定的击穿电压。

公开(公告)号：US07785974B2

公开(公告)日：2010-08-31

申请号：US11474824

申请日：2006-06-26

申请人： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

发明人： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

IPC分类号： H01L21/331

CPC分类号： H01L21/74 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/66272

摘要： A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

摘要翻译： 一种用于形成双极晶体管器件的方法包括提供半导体衬底。 在半导体基板上形成氧化物层。 图案化氧化物层以形成露出半导体衬底的一部分的开口。 通过开口将诸如锑的掺杂剂注入到半导体衬底中以形成掩埋层。 去除掩模层的上部以限定薄掩模层。 进行掩埋层扩散处理以在注入的掺杂剂中驱动，同时减轻凹陷形成。

公开(公告)号：US20100032756A1

公开(公告)日：2010-02-11

申请号：US12537326

申请日：2009-08-07

申请人： Sameer P. PENDHARKAR ,  Binghua HU ,  Xinfen CHEN

发明人： Sameer P. PENDHARKAR ,  Binghua HU ,  Xinfen CHEN

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/73 ,  H01L27/092 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/823892 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7322 ,  H01L29/7816 ,  H01L29/7833

摘要： A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

摘要翻译： 公开了一种掩埋层结构，其包括与连接到IC中的组件的相同导电类型的深阱连接的高电压埋层相邻的浮置掩埋层结构。 浮置掩埋层结构围绕高压掩埋层并且延伸埋层的耗尽区以减小掩埋层的侧边缘处的峰值电场。 当浮动掩埋层结构的尺寸和间距被优化时，连接到掩埋层的阱可被偏压到100伏而不会破坏。 添加围绕第一浮动掩埋层结构的第二浮动掩埋层结构允许埋入层的操作高达140伏。 具有浮动掩埋层结构的掩埋层结构可以并入DEPMOS晶体管，LDMOS晶体管，埋地集电极npn双极晶体管和隔离CMOS电路中。

公开(公告)号：US20090191688A1

公开(公告)日：2009-07-30

申请号：US12020957

申请日：2008-01-28

申请人： Binghua Hu ,  Billy A. Wofford ,  Tan Q. Pham

发明人： Binghua Hu ,  Billy A. Wofford ,  Tan Q. Pham

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method for making STI structure includes etching a STI trench through a nitride layer, through an oxide layer, and into a silicon layer. The method also includes forming a sacrificial liner, pulling-back the nitride layer, and removing a remaining portion of the sacrificial liner. Furthermore, the method includes forming a STI liner and forming a STI fill coupled to the STI liner.

摘要翻译： 制造STI结构的方法包括通过氮化物层，通过氧化物层蚀刻STI沟槽并且进入硅层。 该方法还包括形成牺牲衬垫，拉回氮化物层，以及去除牺牲衬垫的剩余部分。 此外，该方法包括形成STI衬垫并形成耦合到STI衬套的STI填充物。

公开(公告)号：US20090170317A1

公开(公告)日：2009-07-02

申请号：US12100118

申请日：2008-04-09

申请人： Kyle P. Hunt ,  Leila Elvira Noriega ,  Billy Alan Wofford ,  Asadd M. Hosein ,  Binghua Hu ,  Xinfen Chen

发明人： Kyle P. Hunt ,  Leila Elvira Noriega ,  Billy Alan Wofford ,  Asadd M. Hosein ,  Binghua Hu ,  Xinfen Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/31051 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/76229 ,  H01L21/76232

摘要： A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

摘要翻译： 提供了一种用于半导体处理的方法，其中具有下面的主体的工件和从其延伸的多个特征被提供。 所述多个特征的第一组从下面的本体延伸到第一平面，并且所述多个特征的第二组从下面的本体延伸到第二平面。 保护层覆盖多个特征中的每一个，并且隔离层覆盖下面的主体和保护层，其中隔离具有与其相关联的不均匀的第一氧化物密度。 基于预定图案各向异性蚀刻，然后各向同性蚀刻的隔离层，其中隔离层的第二氧化物密度在整个工件上基本均匀。 该预定图案至少部分地基于期望的氧化物密度，多个特征到第一和第二平面的位置和延伸。