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    JFET having width defined by trench isolation
    3.
    发明授权
    JFET having width defined by trench isolation 有权
    JFET具有由沟槽隔离限定的宽度

    公开(公告)号：US09076760B2

    公开(公告)日：2015-07-07

    申请号：US13597439

    申请日：2012-08-29

    申请人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

    发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

    IPC分类号： G01R31/26 ,  H01L29/417 ,  H01L21/00 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10

    CPC分类号： H01L29/41725 ,  G06F2101/00 ,  G06F2201/00 ,  H01L21/00 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/808

    摘要： A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

    摘要翻译： 结型场效应晶体管（JFET）包括具有包括顶侧表面的第一类型半导体表面的衬底和形成在半导体表面中的第二类型的顶栅。 第一型漏极和第一型源形成在顶栅的相对侧上。 第一深沟槽隔离区域具有围绕顶部栅极，漏极和源极的内部第一沟槽壁和外部第一沟槽壁，并且从顶侧表面垂直延伸到深沟槽深度。 形成在半导体表面中的第二类型沉降片在外部第一沟槽壁的外侧横向延伸。 沉降片从顶侧表面垂直延伸到第二类型深部，该深部位于深沟槽深度的下方并且在内部第一沟槽壁的横向内部以提供底部门。

    MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION
    4.
    发明申请
    MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
    具有栅极扩展的MOS晶体管与漏极扩展场绝缘相邻

    公开(公告)号：US20110111569A1

    公开(公告)日：2011-05-12

    申请号：US13006589

    申请日：2011-01-14

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

    MOS transistor with gate trench adjacent to drain extension field insulation
    5.
    发明授权
    MOS transistor with gate trench adjacent to drain extension field insulation 有权
    MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻

    公开(公告)号：US07893499B2

    公开(公告)日：2011-02-22

    申请号：US12417810

    申请日：2009-04-03

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

    MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation
    6.
    发明申请
    MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation 有权
    MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻

    公开(公告)号：US20100252882A1

    公开(公告)日：2010-10-07

    申请号：US12417810

    申请日：2009-04-03

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

    METHODS FOR PREPARING AND DEVICES WITH TREATED DUMMY MOATS
    7.
    发明申请
    METHODS FOR PREPARING AND DEVICES WITH TREATED DUMMY MOATS 有权
    用于制备和装置与处理的DUMMY MOATS的方法

    公开(公告)号：US20090166875A1

    公开(公告)日：2009-07-02

    申请号：US11968085

    申请日：2007-12-31

    申请人： SAMEER PENDHARKAR ,  Binghua Hu

    发明人： SAMEER PENDHARKAR ,  Binghua Hu

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207

    摘要： Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained.

    摘要翻译： 提供了设备和方法以在衬底上的隔离区域中制造虚设的护城河。 目前，在硅化处理之后，假山羊容易失去阻抗。 在高压设备中，硅化虚拟护城河降低了活性区域之间的击穿电压，特别是当虚拟护套重叠或接近结点时。 本发明的装置和方法公开了覆盖有氧化物层的虚拟护城河。 在硅化过程中，虚拟护城河和其他指定的隔离区域保持非硅化。 因此，保持高且稳定的击穿电压。

    HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN
    9.
    发明申请
    HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN 有权
    使用稀释漏水的高压晶体管

    公开(公告)号：US20110309440A1

    公开(公告)日：2011-12-22

    申请号：US13160759

    申请日：2011-06-15

    申请人： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

    发明人： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

    摘要： An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

    摘要翻译： 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

    SURFACE PATTERNED TOPOGRAPHY FEATURE SUITABLE FOR PLANARIZATION
    10.
    发明申请
    SURFACE PATTERNED TOPOGRAPHY FEATURE SUITABLE FOR PLANARIZATION 有权
    表面图案特征适用于平面化

    公开(公告)号：US20080246117A1

    公开(公告)日：2008-10-09

    申请号：US11696829

    申请日：2007-04-05

    申请人： Sameer Pendharkar ,  Binghua Hu ,  Xinfen Celia Chen

    发明人： Sameer Pendharkar ,  Binghua Hu ,  Xinfen Celia Chen

    IPC分类号： H01L21/4763 ,  H01L21/04 ,  H01L29/72

    CPC分类号： H01L29/7322 ,  H01L23/544 ,  H01L29/41708 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

    摘要翻译： 一种用于制造半导体器件的方法，包括在衬底的阱区中注入第一掺杂剂类型以形成由所述阱区的非植入区域分离的注入的子区。 该方法还包括在阱区上形成氧化物层，使得注入的子区域的氧化物转化的第一厚度大于非植入区域的氧化物转化的第二厚度。 该方法还包括去除氧化物层以在阱区上形成形貌特征。 地形特征包括较高和较低部分的表面图案。 更高的部分对应于非植入区域的位置，并且下部对应于植入的子区域。