Optical device including gate insulating layer having edge effect
    11.
    发明授权
    Optical device including gate insulating layer having edge effect 有权
    光学器件包括具有边缘效应的栅极绝缘层

    公开(公告)号:US07924492B2

    公开(公告)日:2011-04-12

    申请号:US12374261

    申请日:2007-04-24

    CPC classification number: G02F1/025 G02F2203/50 G11C13/04

    Abstract: Provided is an optical device having an edge effect with improved phase shift and propagation loss of light without decreasing the dynamic characteristics of the optical device. The optical device includes a first semiconductor layer which is doped with a first type of conductive impurities, and has a recessed groove in an upper portion thereof; a gate insulating layer covering the groove and a portion of the first semiconductor layer; and a second semiconductor layer which covers an upper surface of the gate insulating layer and is doped with a second type of conductive impurities opposite to the first type of conductive impurities.

    Abstract translation: 提供一种具有边缘效应的光学器件,具有改善的相移和光的传播损耗,而不会降低光学器件的动态特性。 光学器件包括掺杂有第一类导电杂质的第一半导体层,并且在其上部具有凹槽; 覆盖所述沟槽和所述第一半导体层的一部分的栅极绝缘层; 以及覆盖所述栅极绝缘层的上表面并且掺杂有与所述第一类型的导电杂质相反的第二类导电杂质的第二半导体层。

    Inductor having high quality factor and unit inductor arranging method thereof
    12.
    发明授权
    Inductor having high quality factor and unit inductor arranging method thereof 有权
    具有高品质因数和单位电感器排列方法的电感器

    公开(公告)号:US06980075B2

    公开(公告)日:2005-12-27

    申请号:US10714287

    申请日:2003-11-13

    CPC classification number: H01L28/10 H01F17/0006 H01L27/08

    Abstract: A method for arranging unit inductors of an inductor having metal wiring that can make a full use of self-inductance and mutual-inductance which are determined based on the proportion of the area of an unit inductor and the proportion of the overlapping area with another unit inductor, and an inductor adopting the unit inductor arranging method. The unit inductor arranging method, wherein the inductor includes a first unit inductor, a second inductor and a third inductor, and self-inductance magnitudes of the unit inductors are in the order of the self-inductance of the third inductor>the self-inductance of the second inductor>the self-inductance of the first inductor, includes the steps of: a) coupling one end of the second unit inductor is connected to one end of the first unit inductor and one end of the third unit inductor to the other end of the first unit inductor in order to arrange the first unit inductor between the second and third unit inductors of which mutual-inductance has the largest value in mutual-inductances between the unit inductors; b) coupling the second unit inductor to a first external terminal; and c) coupling the third unit inductor to a second external terminal.

    Abstract translation: 一种用于布置具有金属布线的电感器的单元电感器的方法,该电感器可以充分利用基于单位电感器的面积的比例和与另一单元的重叠区域的比例确定的自感和互感 电感器和采用单元电感器布置方法的电感器。 单元电感器布置方法,其中电感器包括第一单元电感器,第二电感器和第三电感器,并且单位电感器的自感大小等于第三电感器的自感量>自感 的第二电感器的自感包括以下步骤:a)耦合第二单元电感器的一端连接到第一单元电感器的一端并且将第三单元电感器的一端连接到另一端 从而将第一单元电感器布置在单元电感器之间的互感中互感具有最大值的第二和第三单元电感器之间; b)将第二单元电感器耦合到第一外部端子; 以及c)将所述第三单元电感器耦合到第二外部端子。

    Varactor having improved Q-factor and method of fabricating the same using SiGe heterojunction bipolar transistor
    13.
    发明授权
    Varactor having improved Q-factor and method of fabricating the same using SiGe heterojunction bipolar transistor 有权
    具有改进的Q因子的变容二极管及其使用SiGe异质结双极晶体管的制造方法

    公开(公告)号:US06686640B2

    公开(公告)日:2004-02-03

    申请号:US10044107

    申请日:2002-01-11

    CPC classification number: H01L29/66174 H01L29/66242 H01L29/93

    Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

    Abstract translation: 变容二极管包括第一导电类型的半导体衬底,形成在半导体衬底的上部的第二导电类型的高浓度集电区,在第一表面上形成第二导电类型的集电极区 浓度埋集电极区域,形成在高浓度埋集体区域的第二表面上的第二导电类型的高浓度集电极接触区域,形成在集电体上的第一导电类型的高浓度硅 - 锗基区域 形成在硅 - 锗基区上的金属硅化物层,形成为与金属硅化物层接触的第一电极层和形成为与集电极接触区电连接的第二电极层。

    Photo detector having coupling capacitor
    14.
    发明授权
    Photo detector having coupling capacitor 有权
    具有耦合电容的光电检测器

    公开(公告)号:US08742316B2

    公开(公告)日:2014-06-03

    申请号:US12942338

    申请日:2010-11-09

    CPC classification number: G01J1/46

    Abstract: Provided is a photo detector. The photo detector includes: an avalanche photodiode; a bias circuit supplying a bias voltage to one end of the avalanche photodiode; a detection circuit connected to the other end of the avalanche photodiode and detecting a photoelectric current occurring in the avalanche photodiode; and a coupling capacitor connected to the one end or the other end of the avalanche photodiode and supplying a coupling voltage to drive the avalanche photodiode in a Geiger mode.

    Abstract translation: 提供了一种光电检测器。 光电检测器包括:雪崩光电二极管; 将偏置电压提供给雪崩光电二极管的一端的偏置电路; 连接到雪崩光电二极管的另一端并检测在雪崩光电二极管中出现的光电流的检测电路; 以及耦合电容器,其连接到雪崩光电二极管的一端或另一端并提供耦合电压以以盖革模式驱动雪崩光电二极管。

    Optical device including gate insulator with modulated thickness
    15.
    发明授权
    Optical device including gate insulator with modulated thickness 有权
    光学器件包括调制厚度的栅极绝缘体

    公开(公告)号:US07994549B2

    公开(公告)日:2011-08-09

    申请号:US12375343

    申请日:2007-04-24

    CPC classification number: G02F1/025 G02F1/225 G02F1/3132 H01L31/105

    Abstract: Provided is an optical device with improved phase shift and propagation loss of light without decreasing the dynamic characteristics of the optical device. The optical device includes a first semiconductor layer which is doped with a first type of conductive impurities and has a uniform thickness; a gate insulating layer which has a shape and is formed on a portion of the first semiconductor layer and has a thin center portion; and a second semiconductor layer which covers an upper surface of the gate insulating layer and is doped with a second type of conductive impurities opposite to the first type of conductive type impurities.

    Abstract translation: 提供了一种具有改善的相移和光传播损耗的光学器件,而不会降低光学器件的动态特性。 光学器件包括掺杂有第一类导电杂质并具有均匀厚度的第一半导体层; 栅极绝缘层,其具有形状并且形成在所述第一半导体层的一部分上并且具有薄的中心部分; 以及第二半导体层,其覆盖所述栅极绝缘层的上表面并且掺杂有与所述第一类型的导电类型杂质相反的第二类型的导电杂质。

    AVALANCHE PHOTOTECTOR WITH INTEGRATED MICRO LENS
    16.
    发明申请
    AVALANCHE PHOTOTECTOR WITH INTEGRATED MICRO LENS 审中-公开
    AVALANCHE摄影机与集成微距镜头

    公开(公告)号:US20110140168A1

    公开(公告)日:2011-06-16

    申请号:US12769198

    申请日:2010-04-28

    CPC classification number: H01L31/02327 H01L31/1075

    Abstract: Provided is an avalanche photodetector with an integrated micro lens. The avalanche photodetector includes a light absorbing layer on a semiconductor substrate, an amplification layer on the light absorbing layer, a diffusion layer within the amplification layer, and the micro lens disposed corresponding to the diffusion layer. The micro lens includes a first refractive layer and a second refractive layer having a refractive index less than that of the first refractive layer.

    Abstract translation: 提供了具有集成微透镜的雪崩光电探测器。 雪崩光电检测器包括半导体衬底上的光吸收层,光吸收层上的放大层,放大层内的扩散层和对应于扩散层设置的微透镜。 微透镜包括折射率小于第一折射层的折射率的第一折射层和第二折射层。

    PHOTO DETECTOR HAVING COUPLING CAPACITOR
    17.
    发明申请
    PHOTO DETECTOR HAVING COUPLING CAPACITOR 有权
    具有耦合电容器的照相检测器

    公开(公告)号:US20110133059A1

    公开(公告)日:2011-06-09

    申请号:US12942338

    申请日:2010-11-09

    CPC classification number: G01J1/46

    Abstract: Provided is a photo detector. The photo detector includes: an avalanche photodiode; a bias circuit supplying a bias voltage to one end of the avalanche photodiode; a detection circuit connected to the other end of the avalanche photodiode and detecting a photoelectric current occurring in the avalanche photodiode; and a coupling capacitor connected to the one end or the other end of the avalanche photodiode and supplying a coupling voltage to drive the avalanche photodiode in a Geiger mode.

    Abstract translation: 提供了一种光电检测器。 光电检测器包括:雪崩光电二极管; 将偏置电压提供给雪崩光电二极管的一端的偏置电路; 连接到雪崩光电二极管的另一端并检测在雪崩光电二极管中出现的光电流的检测电路; 以及耦合电容器,其连接到雪崩光电二极管的一端或另一端并提供耦合电压以以盖革模式驱动雪崩光电二极管。

    METHODS OF FORMING A COMPOUND SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION REGION
    18.
    发明申请
    METHODS OF FORMING A COMPOUND SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION REGION 有权
    形成包括扩散区域的化合物半导体器件的方法

    公开(公告)号:US20100144123A1

    公开(公告)日:2010-06-10

    申请号:US12508382

    申请日:2009-07-23

    CPC classification number: H01L21/2258

    Abstract: Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.

    Abstract translation: 提供一种形成化合物半导体器件的方法。 在该方法中,在未掺杂的化合物半导体层上形成掺杂剂元素层。 执行退火处理以将掺杂剂元素层中的掺杂剂扩散到未掺杂的化合物半导体层中,从而形成掺杂剂扩散区域。 相对于具有掺杂剂扩散区域的基板,使用液氮进行快速冷却处理。

    PHOTOELECTRIC DEVICE USING PN DIODE AND SILICON INTEGRATED CIRCUIT (IC) INCLUDING THE PHOTOELECTRIC DEVICE
    19.
    发明申请
    PHOTOELECTRIC DEVICE USING PN DIODE AND SILICON INTEGRATED CIRCUIT (IC) INCLUDING THE PHOTOELECTRIC DEVICE 失效
    使用包括光电装置的PN二极管和硅集成电路(IC)的光电装置

    公开(公告)号:US20100002978A1

    公开(公告)日:2010-01-07

    申请号:US12517802

    申请日:2007-08-07

    CPC classification number: H01L31/12 H01L27/144

    Abstract: Provided are a photoelectric device using a PN diode and a silicon integrated circuit (IC) including the photoelectric device. The photoelectric device includes: a substrate; and an optical waveguide formed as a PN diode on the substrate, wherein a junction interface of the PN diode is formed in a direction in which light advances; and an electrode applying a reverse voltage to the PN diode, wherein N-type and P-type semiconductors of the PN diode are doped at high concentrations and the doping concentration of the N-type semiconductor is higher than or equal to that of the P-type semiconductor.

    Abstract translation: 提供了使用PN二极管的光电装置和包括光电装置的硅集成电路(IC)。 光电装置包括:基板; 以及在所述衬底上形成为PN二极管的光波导,其中所述PN二极管的结界面沿光前进的方向形成; 以及向PN二极管施加反向电压的电极,其中PN二极管的N型和P型半导体以高浓度掺杂,并且N型半导体的掺杂浓度高于或等于P 型半导体。

    OPTICAL DEVICE HAVING STRAINED BURIED CHANNEL
    20.
    发明申请
    OPTICAL DEVICE HAVING STRAINED BURIED CHANNEL 有权
    具有应变通道的光学器件

    公开(公告)号:US20090261383A1

    公开(公告)日:2009-10-22

    申请号:US12441381

    申请日:2007-08-17

    CPC classification number: G02F1/025 G02F1/2257 H01L33/0037

    Abstract: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.

    Abstract translation: 提供了具有应变埋入通道区域的光学装置。 该光学器件包括:第一导电类型的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上的与第一导电类型相反的第二导电类型的栅极; 形成在所述半导体衬底下的高密度掺杂剂扩散区,并且掺杂有比所述半导体衬底更高密度的第一导电型掺杂剂; 由半导体材料形成的应变掩埋沟道区域,具有与形成半导体衬底的材料不同的晶格参数,并且在栅极绝缘层和半导体衬底之间延伸以接触高密度掺杂剂扩散区域; 以及形成在栅绝缘层和应变埋入沟道区之间的半导体盖层。

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