公开(公告)号：US06627484B1

公开(公告)日：2003-09-30

申请号：US10274241

申请日：2002-10-18

Applicant: Boon Yong Ang

Inventor： Boon Yong Ang

IPC: H01L2176

CPC classification number: H01L21/76895 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect layer enabling an overall reduction in the silicon real estate occupied by interconnections. The buried interconnect has low resistance and can prevent the formation of unwanted PN junctions through the use of silicides. The buried interconnect and its fabrication method include an S0I wafer that has an oxidation layer formed on top of a semiconductor layer by oxidation, followed by an nitride layer formed on top of the oxide layer which then is selectively etched to form two trenches with regions of different depths. Some regions of the trenches are etched to remove all of the semiconductor layer in the trench to expose the buried oxide layer. In other regions, a thin layer of semiconductor is left at the bottom of the trenches. Next, all of the exposed surfaces of the trenches are oxidized and the oxide at the trench bottom is removed to expose the underlying semiconductor material. The underlying semiconductor material is then silicided to form a buried interconnect. The wafer, including the trenches, is subsequently covered with oxide and chemical-mechanical polishing is used to remove excess oxide outside the trenches.

Abstract translation: 在与半导体器件一起使用的电路制造工艺流程的早期阶段期间，可以将掩埋互连件并入到绝缘体上的半导体晶片上。 掩埋互连提供了附加的互连层，从而可以实现互连所占用的硅片的整体降低。 埋置互连具有低电阻，并且可以通过使用硅化物来防止形成不期望的PN结。 掩埋互连及其制造方法包括：通过氧化在氧化层顶部形成有氧化层的S0I晶片，随后在氧化物层上形成氮化物层，然后选择性地蚀刻以形成两个沟槽， 不同的深度。 蚀刻沟槽的一些区域以去除沟槽中的所有半导体层以露出掩埋氧化物层。 在其他区域，半导体薄层留在沟槽的底部。 接下来，沟槽的所有暴露表面被氧化，并且去除沟槽底部的氧化物以露出下面的半导体材料。 然后将底层半导体材料硅化以形成掩埋互连。 包括沟槽的晶片随后被氧化物覆盖，并且使用化学机械抛光来除去沟槽外的过量氧化物。

公开(公告)号：US06328641B1

公开(公告)日：2001-12-11

申请号：US09496218

申请日：2000-02-01

Applicant: Boon Yong Ang ,  Kenneth R. Harris

Inventor： Boon Yong Ang ,  Kenneth R. Harris

IPC: B24B700

CPC classification number: B24B37/11 ,  B24B9/065 ,  B24B37/013 ,  B24B49/12

Abstract: An outer edge ring of a semiconductor wafer is polished to prevent delamination and peeling-off of at least one layer of material deposited near the outer edge of the semiconductor wafer during fabrication of integrated circuits. The semiconductor wafer is mounted on a wafer chuck, and the wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The outer edge ring has the at least one layer of material that is polished off by the polishing surface of the polishing pad. The polishing surface of the polishing pad may be tapered such that the edge of an upper layer of material that is disposed further from the semiconductor wafer is disposed more inward toward the center of the semiconductor wafer such that the upper layer of material is not likely to delaminate and peel-off away from a lower abutting layer of material on the semiconductor wafer. Furthermore, a photodetector may determine sufficient polishing of the outer edge ring of the semiconductor wafer.

Abstract translation: 抛光半导体晶片的外边缘环，以防止在集成电路的制造期间沉积在半导体晶片的外边缘附近的至少一层材料的分层和剥离。 将半导体晶片安装在晶片卡盘上，并且保持半导体晶片的晶片卡盘旋转，使得半导体晶片旋转。 当半导体晶片旋转时，抛光垫朝向半导体晶片移动。 当抛光垫向半导体晶片移动以抛光半导体晶片的外边缘环时，抛光垫具有面向并接触半导体晶片的外边缘环的抛光表面。 外边缘环具有由抛光垫的抛光表面抛光的至少一层材料。 抛光垫的抛光表面可以是锥形的，使得更远离半导体晶片的材料的上层的边缘更靠近半导体晶片的中心设置，使得上层材料不可能 从半导体晶片上的下部邻接材料层剥离和剥离。 此外，光电检测器可以确定半导体晶片的外边缘环的充分抛光。

公开(公告)号：US07923785B2

公开(公告)日：2011-04-12

申请号：US10643461

申请日：2003-08-18

Applicant: Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

Inventor： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

Abstract translation: 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

公开(公告)号：US07688639B1

公开(公告)日：2010-03-30

申请号：US11974361

申请日：2007-10-12

Applicant: Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

IPC: G11C16/06

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US20090224323A1

公开(公告)日：2009-09-10

申请号：US12043914

申请日：2008-03-06

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H01L23/62 ,  H01L21/336

CPC classification number: H01L27/101 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract translation: MOS熔丝的至少一个MOS参数的特征在于提供至少一个MOS参数参考值。 然后，通过向熔丝端子施加编程信号来编程MOS熔丝，使得编程电流流过熔丝链。 测量熔丝电阻以提供与第一逻辑值相关联的测量的熔丝电阻。 测量编程的MOS保险丝的MOS参数，以提供测量的MOS参数值。 将测量的MOS参数值与参考MOS参数值进行比较，以确定MOS熔丝的第二逻辑值，并且基于比较输出位值。

公开(公告)号：US07724600B1

公开(公告)日：2010-05-25

申请号：US12043091

申请日：2008-03-05

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: An integrated circuit includes an electronic fuse (“E-fuse”) cell having a fuse link and an E-fuse programming current generator. The fuse link has a width (FLw) and a thickness (FLT) and is fabricated from a layer of link material. An E-fuse programming current generator includes a reference link array having a plurality of reference links. Each of the reference links has the fuse link width and the fuse link thickness, and is fabricated from the layer of link material.

Abstract translation: 集成电路包括具有熔丝链的电子熔丝（“E-fuse”）单元和E熔丝编程电流发生器。 熔断体具有宽度（FLw）和厚度（FLT），并且由一层连接材料制成。 电子熔丝编程电流发生器包括具有多个参考链路的参考链路阵列。 每个参考链路具有熔丝链路宽度和熔丝链路厚度，并且由链路材料层制成。

公开(公告)号：US07710813B1

公开(公告)日：2010-05-04

申请号：US12043099

申请日：2008-03-05

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Raymond C. Pang ,  Boon Yong Ang ,  Serhii Tumakha

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Raymond C. Pang ,  Boon Yong Ang ,  Serhii Tumakha

IPC: G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.

Abstract translation: 电子熔丝存储器阵列具有带有多个可选单元单元的阵列芯。 单元电池具有熔丝和单元晶体管（M12）。 编程电流路径通过熔丝和单元晶体管到字线接地，并且读电流路径也穿过熔丝和单元晶体管到字线地。

公开(公告)号：US07598749B1

公开(公告)日：2009-10-06

申请号：US11449171

申请日：2006-06-08

Applicant: Boon Yong Ang ,  Sunhom Paak ,  Hsung Jai Im ,  Kwansuhk Oh ,  Raymond C. Pang

Inventor： Boon Yong Ang ,  Sunhom Paak ,  Hsung Jai Im ,  Kwansuhk Oh ,  Raymond C. Pang

IPC: G01R31/07 ,  H01L29/00

CPC classification number: G01R31/07 ,  G01R31/31717 ,  G11C29/02 ,  G11C29/027

Abstract: An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.

Abstract translation: 具有efuse链路的efuse的集成电路包括相对于efuse设置的损坏检测结构，以便检测由于对efuse进行编程而导致的IC中的损坏。 IC上可选地包含损伤感测电路。 在评估晶片中使用实施例来确定适当的efuse制造和编程参数，并且在生产IC中用于识别可能产生潜在缺陷的efuse编程损伤。

公开(公告)号：US07294888B1

公开(公告)日：2007-11-13

申请号：US11240030

申请日：2005-09-30

Applicant: Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US20060006552A1

公开(公告)日：2006-01-12

申请号：US10887585

申请日：2004-07-08

Applicant: Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon Chan ,  Cinti Chen

Inventor： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon Chan ,  Cinti Chen

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042

Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Abstract translation: 根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。 该结构还包括位于金属焊盘上的层间电介质层。 该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。 端子通孔仅沿着金属焊盘的一侧延伸。 该结构还包括位于层间电介质层和端子通孔中的端子金属层。 所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。 层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。