公开(公告)号：US20090113546A1

公开(公告)日：2009-04-30

申请号：US12258672

申请日：2008-10-27

Applicant: Sun Kwon KIM ,  Byeong Hoon LEE ,  Ki Hong KIM ,  Hyuck Jun CHO

Inventor： Sun Kwon KIM ,  Byeong Hoon LEE ,  Ki Hong KIM ,  Hyuck Jun CHO

IPC: G06F12/14 ,  G06F12/00 ,  G06F11/00 ,  G11C29/52 ,  G06F12/16

CPC classification number: G11C16/22 ,  G06F11/1068 ,  G06F21/755

Abstract: A memory system includes a main memory, a sub-memory, a controller, first and second data readers and a comparator. The main memory stores data and the sub-memory stores data extracted from the data stored in the main memory for detection of an attack. The controller controls operations of the memory system through interfacing with a host. The first data reader is configured to read first data from the main memory based on address information from the controller. The second data reader is configured to store information relating to second data stored in the sub-memory and to read the second data from the sub-memory based on address information from the controller which is the same as the address information received by the first data reader. The comparator compares the first data read by the first data reader with the second data read by the second data reader to detect the attack.

Abstract translation: 存储器系统包括主存储器，子存储器，控制器，第一和第二数据读取器以及比较器。 主存储器存储数据，子存储器存储从存储在主存储器中的数据中提取的用于检测攻击的数据。 控制器通过与主机连接来控制存储器系统的操作。 第一数据读取器被配置为基于来自控制器的地址信息从主存储器读取第一数据。 第二数据读取器被配置为存储与存储在子存储器中的第二数据相关的信息，并且基于与由第一数据接收的地址信息相同的来自控制器的地址信息从子存储器读取第二数据 读者。 比较器将由第一数据读取器读取的第一数据与由第二数据读取器读取的第二数据进行比较，以检测攻击。

公开(公告)号：US07499322B2

公开(公告)日：2009-03-03

申请号：US11734082

申请日：2007-04-11

Applicant: Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

Inventor： Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

IPC: G11C16/04

CPC classification number: G11C11/412 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002

Abstract: An integrated circuit memory system includes an integrated circuit device having a random access memory array, a non-volatile memory array (e.g., flash memory array) and a data transfer circuit therein. The memory arrays and data transfer circuit may be included in a common integrated circuit chip. The random access memory (RAM) array includes a plurality of columns of RAM cells and a first plurality of bit lines, which are electrically connected to the plurality of columns of RAM cells. The non-volatile memory array includes a plurality of columns of non-volatile memory cells and a second plurality of bit lines, which are electrically connected to a plurality of columns of non-volatile memory cells. The data transfer circuit is electrically connected to the first and second pluralities of bit lines. The data transfer circuit is configured to support direct bidirectional communication between the first and second pluralities of bit lines.

Abstract translation: 集成电路存储器系统包括具有随机存取存储器阵列，非易失性存储器阵列（例如闪存阵列）和其中的数据传输电路的集成电路器件。 存储器阵列和数据传输电路可以包括在公共集成电路芯片中。 随机存取存储器（RAM）阵列包括多个RAM单元列和第一多个位线，它们电连接到多个RAM单元列。 非易失性存储器阵列包括多列非易失性存储器单元和第二多个位线，其电连接到多列非易失性存储器单元。 数据传输电路电连接到第一和第二多个位线。 数据传输电路被配置为支持第一和第二多个位线之间的直接双向通信。

公开(公告)号：US07489557B2

公开(公告)日：2009-02-10

申请号：US11691703

申请日：2007-03-27

Applicant: Sun-Kwon Kim ,  Byeong-Hoon Lee

Inventor： Sun-Kwon Kim ,  Byeong-Hoon Lee

IPC: G11C11/03

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A method of operating a non-volatile memory device includes maintaining a write voltage at a predetermined voltage level for programming and/or erasing a memory cell of the non-volatile memory device during a time between execution of consecutive write operations. For example, the write voltage may be activated at the predetermined voltage level responsive to an initial write command, and discharge of the write voltage may be prevented responsive to a signal indicating consecutive write commands. Related devices are also discussed.

Abstract translation: 一种操作非易失性存储器件的方法包括将写入电压保持在预定电压电平，以便在执行连续写入操作之间的时间期间编程和/或擦除非易失性存储器件的存储器单元。 例如，可以响应于初始写入命令​​在预定电压电平下激活写入电压，并且可以根据指示连续写入命令的信号来防止写入电压的放电。 还讨论了相关设备。

公开(公告)号：US07453304B2

公开(公告)日：2008-11-18

申请号：US11615104

申请日：2006-12-22

Applicant: Sun-Kwon Kim ,  Byeong Hoon Lee

Inventor： Sun-Kwon Kim ,  Byeong Hoon Lee

IPC: G06F1/04

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit for generating a clock signal includes a voltage conversion unit, a maximum power determination unit, a clock control unit and a clock generator. The voltage conversion unit converts an external power supply voltage into an internal power supply voltage and detects a variance in current consumption of a functional block to generate a detected voltage wherein the functional block consumes a predetermined current using the internal power supply voltage. The maximum power determination unit determines a maximum current consumption of the functional block and converts the maximum current consumption to a corresponding maximum allowed voltage. The clock control unit generates at least one frequency control signal based on a comparison between the detected voltage and the maximum allowed voltage. The clock generator generates the clock signal whose frequency is adjusted according to the frequency control signal.

Abstract translation: 用于产生时钟信号的集成电路包括电压转换单元，最大功率确定单元，时钟控制单元和时钟发生器。 电压转换单元将外部电源电压转换为内部电源电压，并检测功能块的电流消耗的变化，以产生检测电压，其中功能块使用内部电源电压消耗预定电流。 最大功率确定单元确定功能块的最大电流消耗，并将最大电流消耗转换为对应的最大允许电压。 时钟控制单元基于检测到的电压和最大允许电压之间的比较产生至少一个频率控制信号。 时钟发生器产生频率根据频率控制信号进行调整的时钟信号。

公开(公告)号：US20080195916A1

公开(公告)日：2008-08-14

申请号：US12010244

申请日：2008-01-23

Applicant: Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G11C29/00

CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0411

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.

Abstract translation: 示例性实施例提供了一种在包括多个存储器单元的非易失性存储器件内由于电荷损失而校正误差数据的方法和装置。 校正非易失性存储器件中的错误数据的方法可以包括通过将响应于第一电压的存储器单元读取的第一数据组与从存储器单元读取的第二数据组进行响应来检测第二数据组中的错误数据 到第二电压。 第二电压高于第一电压。 通过纠错码（ECC）检测第一数据组中的错误数据。 通过对第一数据组中的错误数据和第二数据组中的错误数据进行校正，来重新写入存储器单元中的数据。 中央处理单元（CPU）可以检测第二数据组中的错误。 可以通过页缓冲器读取第二数据组，并与存储在SRAM中的第一数据组进行比较。 检测到的错误可能更新到页面缓冲区。 第一个数据组中的错误数据可能更新到页面缓冲区。 CPU更正最终错误数据中的错误，并且页缓冲区重写多个存储单元中的校正数据。

公开(公告)号：US20080183954A1

公开(公告)日：2008-07-31

申请号：US12016680

申请日：2008-01-18

Applicant: Seung-won LEE ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won LEE ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G06F12/02

CPC classification number: G06F13/4239

Abstract: An apparatus and method for controlling an embedded NAND flash memory. The apparatus includes a code memory storing code information for controlling an access to a NAND flash memory. A register stores code information corresponding to a command to be executed by the NAND flash memory. A central processing unit (CPU) reads the code information corresponding to the command to be executed by the NAND flash memory from the code memory and stores the read code information in the register. A hard-wired logic circuit performs the NAND flash memory access according to the code information stored in the register.

Abstract translation: 一种用于控制嵌入式NAND闪速存储器的装置和方法。 该装置包括存储用于控制对NAND快闪存储器的访问的代码信息的代码存储器。 寄存器存储与由NAND闪存执行的命令对应的代码信息。 中央处理单元（CPU）从代码存储器读取与NAND闪存要执行的命令对应的代码信息，并将读取的代码信息存储在寄存器中。 硬接线逻辑电路根据存储在寄存器中的代码信息执行NAND闪速存取存取。

公开(公告)号：US20080109682A1

公开(公告)日：2008-05-08

申请号：US11869990

申请日：2007-10-10

Applicant: Sun-Kwon KIM ,  Byeong-Hoon LEE ,  Ki-Hong KIM

Inventor： Sun-Kwon KIM ,  Byeong-Hoon LEE ,  Ki-Hong KIM

IPC: G06F11/30 ,  G06F9/44

CPC classification number: G06F11/00

Abstract: An integrated circuit card includes a central processing unit, a memory and an abnormal condition detector. The memory stores data to be processed by the central processing unit. The abnormal condition detector detects whether at least one operating condition of the integrated circuit card is within one of a suspend region or a reset region. The abnormal condition detector controls an operation of the central processing unit in accordance with the detection.

Abstract translation: 集成电路卡包括中央处理单元，存储器和异常状态检测器。 存储器存储要由中央处理单元处理的数据。 异常状况检测器检测集成电路卡的至少一个工作状态是否在暂停区域或复位区域中的一个内。 异常状态检测器根据检测器控制中央处理单元的操作。

公开(公告)号：US07083198B2

公开(公告)日：2006-08-01

申请号：US10649896

申请日：2003-08-28

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/18 ,  B62D1/184 ,  B62D1/187

CPC classification number: B62D1/184

Abstract: A tilt steering apparatus for a vehicle includes a lower steering shaft of which the low end is mounted with a steering gear, an upper steering shaft of which the upper end is mounted with a steering wheel. A universal joint joins a top end of the lower steering shaft with a lower end of the upper steering shaft and a lower column member is fixed to a vehicle body to support the lower steering shaft to be moveable. An upper column member supports the upper steering shaft to be moveable and a tilt lock mechanism that tilt locks the upper column member to the lower column member is provided. The tilt lock mechanism includes a fixed gear attached to the lower column member and a moveable gear attached to the upper column member so as to be moveable. A female gear is provided on the upper column member and a feed screw bar is mounted to the female member to lock the moveable gear to the fixed gear by pressing the moveable gear.

Abstract translation: 用于车辆的倾斜转向装置包括下转向轴，其下端安装有舵机，上转向轴的上端安装有方向盘。 万向接头将下转向轴的顶端与上转向轴的下端连接，下柱构件固定在车体上，以支撑下转向轴可移动。 上柱构件支撑上转向轴可移动，并且提供倾斜锁定机构，其倾斜将上柱构件锁定到下柱构件。 倾斜锁定机构包括附接到下柱构件的固定齿轮和附接到上柱构件以便可移动的可移动齿轮。 在上柱构件上设置有母齿轮，并且通过按压可移动齿轮将进给螺杆安装到阴构件以将可移动齿轮锁定到固定齿轮。

公开(公告)号：US20060139073A1

公开(公告)日：2006-06-29

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US07052043B2

公开(公告)日：2006-05-30

申请号：US10649860

申请日：2003-08-28

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/18

CPC classification number: B62D1/184 ,  B62D1/187

Abstract: A tilt steering apparatus for a vehicle includes a lower steering shaft of which low end being mounted with a steering gear, an upper steering shaft of which top end being mounted with a steering wheel, a universal joint that joints a top end of the lower steering shaft with a low end of the upper steering shaft, a lower column member fixed to a vehicle body to support the lower steering shaft to be pivotable, an upper column member that supports the upper steering shaft to be pivotable, and a tilt lock mechanism that tilt-locks the upper column member to the lower column member. The top end side of the upper column member is closed.

Abstract translation: 一种用于车辆的倾斜转向装置包括：下转向轴，其下端安装有舵机;上转向轴，其顶端安装有方向盘;万向接头，其连接下转向器的顶端 轴，其具有上转向轴的低端，固定到车体以支撑下转向轴可枢转的下柱构件，支撑上转向轴以可枢转的上柱构件和倾斜锁定机构， 将上柱构件倾斜锁定到下柱构件。 上柱构件的顶端侧封闭。