Abstract:
A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.
Abstract:
A custom assembly light-emitting module using plugs and jacks for obtaining vertical electrical connections, includes a light-emitting unit, a lens unit, a plug unit and a jack unit. The lens unit is detachably combined with the light-emitting unit. The plug unit is disposed beside one side of the lens unit and electrically connected with the light-emitting unit. The jack unit is disposed on a bottom side of the plug unit and electrically connected with the plug unit. In addition, the light-emitting unit has two first retaining structures being formed on two opposite lateral sides thereof, the lens unit has a hollow transparent structure and a lens integratedly with the hollow transparent structure, two second retaining structures are disposed in the hollow transparent structure, and the light-emitting unit is detachably disposed in the hollow transparent structure.
Abstract:
An embedded chip package includes a substrate, a semiconductor structure, an encapsulating material layer and a plurality of conductive vias. Herein the substrate includes at least a dielectric layer and at least a patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate and has a plurality of electrical bonding pads, and the electrical bonding pads contact the dielectric layer. The encapsulating material layer is disposed on the substrate and around the semiconductor structure. In addition, a plurality of conductive vias is disposed in the substrate to electrically connect the patterned circuit layer to the electrical bonding pads.
Abstract:
A three-dimensionally vibration-preventing buffering mechanism is proposed, which is designed for use in conjunction with a dynamic module for the purpose of buffering the three dimensional vibrations of the dynamic module during operation, and which is characterized by the use of a group of specially-designed chained elastic members, each being composed of at least three integrally-linked flexure hinges whose axes of concavity are oriented respectively in parallel with the three axes of a three-dimensional rectangular coordinate system, so that the vibrations of the dynamic module in all three dimensional directions can be respectively buffered by these flexure hinges to provide a three-dimensional vibration-preventing buffering effect.
Abstract:
A cable collector of a power supply apparatus is provided. The power supply apparatus includes a power adaptor, a cable, and a cable collector. One side of the cable is connected with the power adaptor. The cable collector includes a first board, a first power connector, and two first blocking boards. The first board is connected with a first surface of the power adaptor. The first power connector is formed on the first board. The first board is connected with the power adaptor via the first power connector. The two first blocking boards are formed on two sides of the first board.
Abstract:
The invention discloses a testing system and a testing method. The testing system includes a testing platform and a fetching device. The testing platform includes a metal base plate, a DUT board, a testing stand and a metal wall. The DUT board is disposed on the metal base plate. The testing stand is disposed on the DUT board. The metal wall is disposed on the metal base plate and surrounds the testing stand. The fetching device is movably disposed above the testing platform and used for placing a DUT on the testing stand. A metal covering plate of the fetching device corresponds to the metal wall of the testing platform. When the fetching device places the DUT on the testing stand, the metal covering plate cooperates with the metal wall and the metal base plate of the testing platform to form an isolated space, so as to isolate the DUT.
Abstract:
A cable collector of a power supply apparatus is provided. The power supply apparatus includes a power adaptor, a cable, and a cable collector. One side of the cable is connected with the power adaptor. The cable collector includes a first board, a first power connector, and two first blocking boards. The first board is connected with a first surface of the power adaptor. The first power connector is formed on the first board. The first board is connected with the power adaptor via the first power connector. The two first blocking boards are formed on two sides of the first board.
Abstract:
A beverage product comprising at least one beverage base and at least one polyunsaturated fatty acid emulsion, said emulsion comprising a continuous liquid phase; an emulsifier; and a discontinuous liquid phase comprising a blend including a polyunsaturated fatty acid source and a dispersing agent, the polyunsaturated fatty acid source comprising at least one polyunsaturated fatty acid, wherein the weight ratio of the fatty acid source to the dispersing agent in the blend ranges from about 9:1 to about 1:10.
Abstract:
A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will peel or the sacrificial layer material will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.
Abstract:
A device and method for block code error correction. The device includes a block code input unit, an erasing address table, an error table and a decoder. The block code input unit is used to input a block code. The erasing address table and the error table have a plurality of erasing entities and error entities in rows and columns, respectively. The decoder decodes the block code in a row direction based on the erasing address table to find data errors on rows and update the error table, and updates the erasing address table in the row direction according to a first determination principle. Next, the decoder decodes the block code in a column direction based on the erasing address table to find data errors on columns and update the error table, and updates the erasing address table in the column direction according to a second determination principle.