公开(公告)号：US08044913B2

公开(公告)日：2011-10-25

申请号：US11833840

申请日：2007-08-03

Applicant: Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

Inventor： Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0443 ,  G09G2310/0289 ,  G09G2310/06

Abstract: A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

Abstract translation: 公开了用于驱动显示装置的栅极驱动器。 所述栅极驱动器包括：第一输入缓冲器，被配置为用于接收参考电压并输出第一缓冲电压;控制电路，被配置为输出多个扫描启动信号和补偿启动信号，多个补偿输出缓冲器， 和多个扫描输出缓冲器。 多个补偿输出缓冲器中的每一个被配置为分别接收补偿起始信号之一并分别输出补偿信号，其中每个补偿输出缓冲器接收第一缓冲电压作为功率。 多个扫描输出缓冲器中的每一个被配置为分别接收扫描起始信号之一并输出扫描信号。

公开(公告)号：US07812803B2

公开(公告)日：2010-10-12

申请号：US11760156

申请日：2007-06-08

Applicant: Yen-Chen Chen ,  Chien-Pin Chen ,  Chia-Cheng Lai

Inventor： Yen-Chen Chen ,  Chien-Pin Chen ,  Chia-Cheng Lai

IPC: G09G3/36

CPC classification number: G09G3/3622 ,  G09G2300/0486

Abstract: The present invention relates to a driving method for cholesteric liquid crystal display. A plurality of pixels of the display are controlled by a plurality of row drivers and a plurality of column drivers. According to the method of the invention, firstly, a DC input voltage or a non-symmetric AC input voltage is applied to the row drivers and the column drivers so that the voltage of the pixel is larger than a withstand voltage of the drivers. Then, an initial column signal and an initial row signal are respectively supplied by the corresponding column driver and row driver so as to initialize the corresponding pixel. The polarity of the initial column signal is different from that of the initial row signal. Because the initial row signal minus the initial column signal equals the signal of the pixel, the amplitude of the signal applied to the pixel can be increased. Therefore, according to the invention, the initial time of the pixel can be decreased, and the transferring speed of the pixel can be improved.

Abstract translation: 本发明涉及胆甾型液晶显示器的驱动方法。 显示器的多个像素由多个行驱动器和多个列驱动器控制。 根据本发明的方法，首先，对行驱动器和列驱动器施加DC输入电压或非对称AC输入电压，使得像素的电压大于驱动器的耐受电压。 然后，相应的列驱动器和行驱动器分别提供初始列信号和初始行信号，以初始化对应的像素。 初始列信号的极性与初始行信号的极性不同。 由于初始行信号减去初始列信号等于像素的信号，所以可以增加施加到像素的信号的幅度。 因此，根据本发明，可以减少像素的初始时间，并且可以提高像素的传送速度。

公开(公告)号：US20090134901A1

公开(公告)日：2009-05-28

申请号：US11946053

申请日：2007-11-28

Applicant: Ping-Po Chen ,  Chien-Pin Chen

Inventor： Ping-Po Chen ,  Chien-Pin Chen

IPC: G01R31/26 ,  H01L23/58

CPC classification number: G11C29/48 ,  G11C29/1201 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: By adding multiplexing units to selectively transmit signals associated with a functional circuitry of an IC die to test pads, a probe card with less pin counts than the pad number of the IC die can be utilized for testing the functional circuitry. Therefore, the pad number/pad pitch of the IC die is not limited by the pitch of the conventional probe card. A high pin count IC die design is thereby available.

Abstract translation: 通过添加复用单元来选择性地将与IC芯片的功能电路相关联的信号传输到测试焊盘，可以利用具有比IC芯片的焊盘编号更少引脚数的探针卡来测试功能电路。 因此，IC芯片的焊盘编号/焊盘间距不受常规探针卡的间距的限制。 因此可以获得高引脚数IC管芯设计。

公开(公告)号：US20080231582A1

公开(公告)日：2008-09-25

申请号：US11833840

申请日：2007-08-03

Applicant: Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

Inventor： Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0443 ,  G09G2310/0289 ,  G09G2310/06

Abstract: A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

Abstract translation: 公开了用于驱动显示装置的栅极驱动器。 所述栅极驱动器包括：第一输入缓冲器，被配置为用于接收参考电压并输出第一缓冲电压;控制电路，被配置为输出多个扫描启动信号和补偿启动信号，多个补偿输出缓冲器， 和多个扫描输出缓冲器。 多个补偿输出缓冲器中的每一个被配置为分别接收补偿起始信号之一并分别输出补偿信号，其中每个补偿输出缓冲器接收第一缓冲电压作为功率。 多个扫描输出缓冲器中的每一个被配置为分别接收扫描起始信号之一并输出扫描信号。

公开(公告)号：US20080093737A1

公开(公告)日：2008-04-24

申请号：US11551942

申请日：2006-10-23

Applicant: Chan-Liang Wu ,  Ming-Cheng Chiu ,  Chien-Pin Chen

Inventor： Chan-Liang Wu ,  Ming-Cheng Chiu ,  Chien-Pin Chen

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.

Abstract translation: 公开了一种具有减小的焊盘凸起区域的集成电路及其制造方法。 集成电路包括半导体衬底，互连层，钝化层和至少一个凸块。 半导体衬底上具有半导体器件。 互连层设置在半导体衬底上并顶上顶层金属层，该顶层金属层至少包括焊盘和导线。 钝化层设置在互连层上，并具有至少一个露出焊盘的开口。 凸块设置在钝化层上以将焊盘穿过开口连接并且延伸到不直接在焊盘上方的覆盖区域。

公开(公告)号：US06806515B2

公开(公告)日：2004-10-19

申请号：US10044950

申请日：2002-01-15

Applicant: Chuan-Cheng Hsiao ,  Lin-Kai Bu ,  Kun-Cheng Hung ,  Chien-Pin Chen

Inventor： Chuan-Cheng Hsiao ,  Lin-Kai Bu ,  Kun-Cheng Hung ,  Chien-Pin Chen

IPC: H01L31072

CPC classification number: H01L27/0207 ,  G02F1/1368 ,  G09G3/3688 ,  G09G2310/027

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Abstract translation: 提供具有m * n个节点的解码器的布局结构及其方法。 节点包括多个晶体管节点和多个信道节点。 晶体管节点的制造方法包括形成栅极，第一源极/漏极区域和第二源极/漏极区域。 通道节点通过形成通道来制造。 通道，第一源极/漏极区域和第二源极/漏极区域同时用相同的材​​料形成。 具有较小宽度的解码器电路在本发明中实现而不需要额外的掩模。

公开(公告)号：US07830349B2

公开(公告)日：2010-11-09

申请号：US11843723

申请日：2007-08-23

Applicant: Lin-Kai Bu ,  Chien-Pin Chen ,  Hsien-Chang Tsai

Inventor： Lin-Kai Bu ,  Chien-Pin Chen ,  Hsien-Chang Tsai

IPC: G09G3/36

CPC classification number: G09G3/20 ,  G09G2300/0408 ,  G09G2310/0267

Abstract: A gate driving apparatus for driving a pixel array on a panel. The apparatus includes a driver chip having a first transistor with a gate coupled to receive a Nth gate driving signal, a source coupled to receive a first voltage and a drain coupled to a Nth scan line of the pixel array, and a driving circuit formed on the panel, providing a second voltage to the Nth scan line when the first transistor in the driver chip is turned off by the Nth gate driving signal and providing the first voltage to the Nth scan line when the first transistor is turned on by the Nth gate driving signal.

Abstract translation: 一种用于驱动面板上的像素阵列的门驱动装置。 该装置包括具有第一晶体管的驱动器芯片，第一晶体管具有耦合以接收第N栅极驱动信号的栅极，耦合到接收耦合到像素阵列的第N扫描线的第一电压和漏极的源和驱动电路， 面板，当驱动器芯片中的第一晶体管被第N栅极驱动信号截止时，向第N扫描线提供第二电压，并且当第N晶体管被第N栅极导通时，将第一电压提供给第N扫描线 驾驶信号。

公开(公告)号：US20090195526A1

公开(公告)日：2009-08-06

申请号：US12025216

申请日：2008-02-04

Applicant: Chien-Pin Chen ,  Biing-Seng Wu

Inventor： Chien-Pin Chen ,  Biing-Seng Wu

IPC: G06F3/038 ,  G09G3/36

CPC classification number: G09G3/3677 ,  G09G2320/0209

Abstract: A driver integrated circuit (IC) for driving a panel having pixels controlled by gate lines and data lines is disclosed, including a power circuit for generating a high level voltage and a low level voltage, a timing controller, a source driving circuit controlled by the timing controller to drive the data lines, a gate driving circuit controlled by the timing controller to selectively enable one of the gate lines for a line period. The gate driving circuit first asserts the selected gate line with the high level voltage in order to activate the corresponding pixels for receiving the driving signals from the corresponding data lines, and the gate driving circuit subsequently asserts the selected gate line with the low level voltage such that the corresponding pixels are still activated for receiving the driving signals. An LCD device utilizing the driver IC is also provided.

Abstract translation: 公开了一种用于驱动具有由栅极线和数据线控制的像素的面板的驱动器集成电路（IC），包括用于产生高电平电压和低电平电压的电源电路，定时控制器，由 定时控制器，用于驱动数据线，门控驱动电路由定时控制器控制，以选择性地使一个栅极线路线路周期。 栅极驱动电路首先以高电平电压使所选择的栅极线被激活，以便激活对应的像素以从相应的数据线接收驱动信号，并且栅极驱动电路随后以低电平电压确定所选择的栅极线， 相应的像素仍然被激活以接收驱动信号。 还提供了利用驱动器IC的LCD装置。

公开(公告)号：US07541274B2

公开(公告)日：2009-06-02

申请号：US11551942

申请日：2006-10-23

Applicant: Chan-Liang Wu ,  Ming-Cheng Chiu ,  Chien-Pin Chen

Inventor： Chan-Liang Wu ,  Ming-Cheng Chiu ,  Chien-Pin Chen

IPC: H01L21/44 ,  H01L23/52

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.

Abstract translation: 公开了一种具有减小的焊盘凸起区域的集成电路及其制造方法。 集成电路包括半导体衬底，互连层，钝化层和至少一个凸块。 半导体衬底上具有半导体器件。 互连层设置在半导体衬底上并顶上顶层金属层，该顶层金属层至少包括焊盘和导线。 钝化层设置在互连层上，并具有至少一个露出焊盘的开口。 凸块设置在钝化层上以将焊盘穿过开口连接并且延伸到不直接在焊盘上方的覆盖区域。

公开(公告)号：US20100264522A1

公开(公告)日：2010-10-21

申请号：US12702222

申请日：2010-02-08

Applicant: Chien-Pin Chen ,  Chiu-Shun Lin

Inventor： Chien-Pin Chen ,  Chiu-Shun Lin

IPC: H01L23/498 ,  H01L23/28

CPC classification number: H01L23/3192 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor chip, a plurality of bumps and at least one electrically conductive component. The semiconductor chip includes an active area having electronic circuits formed therein and a plurality of pads. The plurality of bumps is placed on the semiconductor chip, wherein a location where at least one of the bumps is located on the semiconductor chip does not overlap a location where a specific pad of the pads is located on the semiconductor chip. The electrically conductive component connects a top surface of at least the bump and the specific pad.

Abstract translation: 半导体器件包括半导体芯片，多个凸块和至少一个导电部件。 半导体芯片包括其中形成有电子电路的有源区和多个焊盘。 多个凸块被放置在半导体芯片上，其中至少一个凸块位于半导体芯片上的位置不与衬垫的特定焊盘位于半导体芯片上的位置重叠。 导电部件连接至少凸起的顶表面和特定焊盘。