公开(公告)号：US20100264522A1

公开(公告)日：2010-10-21

申请号：US12702222

申请日：2010-02-08

Applicant: Chien-Pin Chen ,  Chiu-Shun Lin

Inventor： Chien-Pin Chen ,  Chiu-Shun Lin

IPC: H01L23/498 ,  H01L23/28

CPC classification number: H01L23/3192 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor chip, a plurality of bumps and at least one electrically conductive component. The semiconductor chip includes an active area having electronic circuits formed therein and a plurality of pads. The plurality of bumps is placed on the semiconductor chip, wherein a location where at least one of the bumps is located on the semiconductor chip does not overlap a location where a specific pad of the pads is located on the semiconductor chip. The electrically conductive component connects a top surface of at least the bump and the specific pad.

Abstract translation: 半导体器件包括半导体芯片，多个凸块和至少一个导电部件。 半导体芯片包括其中形成有电子电路的有源区和多个焊盘。 多个凸块被放置在半导体芯片上，其中至少一个凸块位于半导体芯片上的位置不与衬垫的特定焊盘位于半导体芯片上的位置重叠。 导电部件连接至少凸起的顶表面和特定焊盘。

公开(公告)号：US20100109157A1

公开(公告)日：2010-05-06

申请号：US12265439

申请日：2008-11-05

Applicant: Chiu-Shun Lin

Inventor： Chiu-Shun Lin

IPC: H01L23/498

CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/1412 ,  H01L2224/16245 ,  H01L2224/81125 ,  H01L2924/00013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.

Abstract translation: 本文公开了一种芯片结构和芯片封装结构。 芯片结构包括芯片和凸块。 该芯片包括至少一个焊盘。 凸块设置在垫的边界区域上。 凸块的形状是三角柱或梯形柱。 凸起和垫之间的连接表面积小于或等于边界区域。 因此，可以减少材料的使用和冲击的成本。 此外，凸起的这种形状具有方向特性，使得容易通过可识别的焊盘执行芯片测试，并且执行将芯片接合到电路板或任何载体的封装处理。

公开(公告)号：US20090206472A1

公开(公告)日：2009-08-20

申请号：US12057387

申请日：2008-03-28

Applicant: Chiu-Shun Lin ,  Pai-Sheng Cheng

Inventor： Chiu-Shun Lin ,  Pai-Sheng Cheng

IPC: H01L23/04 ,  H01L21/02 ,  H01L21/66

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H05K1/0209 ,  H05K1/189 ,  H05K3/303 ,  H05K2201/0108 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2203/166 ,  Y02P70/613

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract translation: COF包装结构包括基板，第一导电箔和第二导电箔。 基板具有与第一表面相对的第一表面和第二表面。 第一导电箔设置在基板的第一表面上，并且具有用于凸起接合的第一指定图案。 第二导电箔设置在基板的第二表面上，并具有第二指定图案，其中第二指定图案的面积不小于第一指定图案的面积。

公开(公告)号：US20090091028A1

公开(公告)日：2009-04-09

申请号：US12110868

申请日：2008-04-28

Applicant: Chiu-Shun Lin ,  Chia-Hui Wu ,  Wen-Chieh Tu

Inventor： Chiu-Shun Lin ,  Chia-Hui Wu ,  Wen-Chieh Tu

IPC: H01L23/482 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81903 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29075 ,  H01L2224/83851

Abstract: A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central part of the contact pad. The seeding layer is disposed on the exposed central part of the contact pad. The bump has a top surface, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The bump is disposed on the seeding layer. The bump is placed in contact with the seeding layer by the bottom surface and by part of the side surface.

Abstract translation: 提供了包括半导体衬底，接触焊盘，钝化层，凸块和接种层的半导体器件。 半导体衬底具有活性表面。 接触垫设置在有源表面上。 钝化层设置在有源表面上并且暴露接触焊盘的中心部分。 接种层设置在接触垫的暴露的中心部分上。 凸块具有顶表面，与顶表面相对的底表面和连接顶表面和底表面的侧表面。 凸块设置在接种层上。 凸块通过底面和侧面的一部分与接种层接触。

公开(公告)号：US07064449B2

公开(公告)日：2006-06-20

申请号：US10711674

申请日：2004-09-30

Applicant: Chiu-Shun Lin ,  Kuan-Chou Lin ,  Chia-Hui Wu ,  Pai-Sheng Cheng

Inventor： Chiu-Shun Lin ,  Kuan-Chou Lin ,  Chia-Hui Wu ,  Pai-Sheng Cheng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip structure and a bonding pad are provided. The chip structure comprises a chip and at least a bonding pad. The chip has an active surface. The bonding pad is disposed on the active surface of the chip. The bonding pad comprises a polygonal body and a plurality of first protruding portions. The polygonal body has a first planar surface and a corresponding second planar surface. The second planar surface of the polygonal body is in contact with the chip. The first protruding portions are disposed on the first planar surface at the corner regions of the polygonal body. By modifying the geometric shape of the bonding pad, the yield of bonding the chip structure and another device together through the bonding pad is increased.

Abstract translation: 提供了芯片结构和接合焊盘。 芯片结构包括芯片和至少一个焊盘。 该芯片具有活性表面。 焊盘设置在芯片的有源表面上。 接合焊盘包括多边形主体和多个第一突出部分。 多边形体具有第一平面和相应的第二平面。 多边体的第二平面与芯片接触。 第一突出部设置在多边体的角部的第一平面上。 通过改变接合焊盘的几何形状，增加了通过接合焊盘将芯片结构和另一个器件结合在一起的成品率。

公开(公告)号：US08618678B2

公开(公告)日：2013-12-31

申请号：US12265439

申请日：2008-11-05

Applicant: Chiu-Shun Lin

Inventor： Chiu-Shun Lin

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/1412 ,  H01L2224/16245 ,  H01L2224/81125 ,  H01L2924/00013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.

Abstract translation: 本文公开了一种芯片结构和芯片封装结构。 芯片结构包括芯片和凸块。 该芯片包括至少一个焊盘。 凸块设置在垫的边界区域上。 凸块的形状是三角柱或梯形柱。 凸起和垫之间的连接表面积小于或等于边界区域。 因此，可以减少材料的使用和冲击的成本。 此外，凸起的这种形状具有方向特性，使得容易通过可识别的焊盘执行芯片测试，并且执行将芯片接合到电路板或任何载体的封装处理。

公开(公告)号：US07906374B2

公开(公告)日：2011-03-15

申请号：US12057387

申请日：2008-03-28

Applicant: Chiu-Shun Lin ,  Pai-Sheng Cheng

Inventor： Chiu-Shun Lin ,  Pai-Sheng Cheng

IPC: H01L21/00

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H05K1/0209 ,  H05K1/189 ,  H05K3/303 ,  H05K2201/0108 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2203/166 ,  Y02P70/613

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract translation: COF包装结构包括基板，第一导电箔和第二导电箔。 基板具有与第一表面相对的第一表面和第二表面。 第一导电箔设置在基板的第一表面上，并且具有用于凸起接合的第一指定图案。 第二导电箔设置在基板的第二表面上，并具有第二指定图案，其中第二指定图案的面积不小于第一指定图案的面积。

公开(公告)号：US07449770B2

公开(公告)日：2008-11-11

申请号：US11341877

申请日：2006-01-27

Applicant: Chiu-Shun Lin ,  Po-Chiang Tseng ,  Chen-Li Wang ,  Chia-Ying Lee

Inventor： Chiu-Shun Lin ,  Po-Chiang Tseng ,  Chen-Li Wang ,  Chia-Ying Lee

IPC: H01L23/495 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a substrate with slot. The substrate of the invention comprises an active surface and a plurality of metal plates. The metal plates are formed on the active surface. Each metal plate has a first surface and a second surface. The first surface is connected to the active surface. At least one metal plate has at least one slot formed on the second surface. Therefore, according to the substrate with slot of the invention, a resin for connecting a chip and the metal plates can entirely seal sides and corners of the chip so as to prevent water or dust from entering the chip and protect the chip.

Abstract translation: 本发明涉及具有槽的衬底。 本发明的基底包括活性表面和多个金属板。 金属板形成在活性表面上。 每个金属板具有第一表面和第二表面。 第一表面连接到活动表面。 至少一个金属板具有形成在第二表面上的至少一个槽。 因此，根据本发明的具有槽的基板，用于连接芯片和金属板的树脂可以完全密封芯片的两侧和角部，以防止水或灰尘进入芯片并保护芯片。

公开(公告)号：US20060175088A1

公开(公告)日：2006-08-10

申请号：US11341877

申请日：2006-01-27

Applicant: Chiu-Shun Lin ,  Po-Chiang Tseng ,  Chen-Li Wang ,  Chia-Ying Lee

Inventor： Chiu-Shun Lin ,  Po-Chiang Tseng ,  Chen-Li Wang ,  Chia-Ying Lee

IPC: H01L23/495

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a substrate with slot. The substrate of the invention comprises an active surface and a plurality of metal plates. The metal plates are formed on the active surface. Each metal plate has a first surface and a second surface. The first surface is connected to the active surface. At least one metal plate has at least one slot formed on the second surface. Therefore, according to the substrate with slot of the invention, a resin for connecting a chip and the metal plates can entirely seal sides and corners of the chip so as to prevent water or dust from entering the chip and protect the chip.

Abstract translation: 本发明涉及具有槽的衬底。 本发明的基底包括活性表面和多个金属板。 金属板形成在活性表面上。 每个金属板具有第一表面和第二表面。 第一表面连接到活动表面。 至少一个金属板具有形成在第二表面上的至少一个槽。 因此，根据本发明的具有槽的基板，用于连接芯片和金属板的树脂可以完全密封芯片的两侧和角部，以防止水或灰尘进入芯片并保护芯片。

公开(公告)号：US20060006531A1

公开(公告)日：2006-01-12

申请号：US10711674

申请日：2004-09-30

Applicant: Chiu-Shun Lin ,  Kuan-Chou Lin ,  Chia-Hui Wu ,  Pai-Sheng Cheng

Inventor： Chiu-Shun Lin ,  Kuan-Chou Lin ,  Chia-Hui Wu ,  Pai-Sheng Cheng

IPC: H01L23/48

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip structure and a bonding pad are provided. The chip structure comprises a chip and at least a bonding pad. The chip has an active surface. The bonding pad is disposed on the active surface of the chip. The bonding pad comprises a polygonal body and a plurality of first protruding portions. The polygonal body has a first planar surface and a corresponding second planar surface. The second planar surface of the polygonal body is in contact with the chip. The first protruding portions are disposed on the first planar surface at the corner regions of the polygonal body. By modifying the geometric shape of the bonding pad, the yield of bonding the chip structure and another device together through the bonding pad is increased.

Abstract translation: 提供了芯片结构和接合焊盘。 芯片结构包括芯片和至少一个焊盘。 该芯片具有活性表面。 焊盘设置在芯片的有源表面上。 接合焊盘包括多边形主体和多个第一突出部分。 多边形体具有第一平面和相应的第二平面。 多边体的第二平面与芯片接触。 第一突出部设置在多边体的角部的第一平面上。 通过改变接合焊盘的几何形状，增加了通过接合焊盘将芯片结构和另一个器件结合在一起的成品率。