公开(公告)号：US5150079A

公开(公告)日：1992-09-22

申请号：US717238

申请日：1991-06-18

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B2200/0012

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4871982A

公开(公告)日：1989-10-03

申请号：US264193

申请日：1988-10-28

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03K3/014 ,  H03K3/354 ,  H03L3/00

CPC classification number: H03B5/30 ,  H03B5/06 ,  H03K3/014 ,  H03K3/3545 ,  H03L3/00

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4460978A

公开(公告)日：1984-07-17

申请号：US322915

申请日：1981-11-19

Applicant: Ching-Lin Jiang ,  David L. Taylor

Inventor： Ching-Lin Jiang ,  David L. Taylor

IPC: G11C14/00 ,  G11C11/40

CPC classification number: G11C14/00

Abstract: A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the driver transistors (12, 14) and load devices (48, 50). A control node (40) is driven to a high voltage state to cause one of the variable threshold transistors (36, 41) to be driven to have a higher threshold voltage and thereby store the data state held in the cross-coupled transistors (12, 14). The data state is thus stored in nonvolatile form. Upon recall the memory cell (10) is reactivated and the threshold differential between the variable threshold transistors (36, 41) causes the driver transistors (12, 14) to be set at the stored data state. The data recalled by the memory cell (10) is in true rather than in complementary form. The variable threshold transistors (36, 41) are reset by driving the power terminal V.sub.cc to a high voltage state to reestablish common threshold voltages for the variable threshold voltage transistors (36, 41).

Abstract translation: 非易失性静态随机存取存储单元（10）包括一对交叉耦合晶体管（12,14），其作为双稳态电路来存储数据状态。 可变阈值晶体管（36,41）分别串联连接在驱动晶体管（12,14）和负载装置（48,50）之间。 控制节点（40）被驱动到高电压状态以使可变阈值晶体管（36,41）中的一个被驱动以具有较高的阈值电压，从而存储保持在交叉耦合晶体管（12）中的数据状态 ，14）。 数据状态因此以非易失性形式存储。 一旦召回，存储器单元（10）被重新激活，并且可变阈值晶体管（36,41）之间的阈值差使得驱动晶体管（12,14）被设置在存储的数据状态。 由存储器单元（10）调用的数据是真实的而不是互补形式。 通过将电源端子Vcc驱动到高电压状态来重建可变阈值晶体管（36,41），以重建可变阈值电压晶体管（36,41）的公共阈值电压。

公开(公告)号：US4308594A

公开(公告)日：1981-12-29

申请号：US117223

申请日：1980-01-31

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/402 ,  G11C11/412 ,  H01L27/108 ,  H01L29/78 ,  H03K3/356 ,  G11C11/40 ,  G11C11/24

CPC classification number: G11C11/412 ,  G11C11/4023 ,  H01L27/108 ,  H03K3/35606 ,  H03K3/356086

Abstract: An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to the first node (S) and the second node (K) and the second clock line (36). The third transistor (24) provides a charging path between the second clock line (36) and the second node (K) for conditionally maintaining a voltage at the second node (K).

Abstract translation: 提供具有位线（12），字线（14）和单元电压供应（26）的集成电路存储单元（10）。 集成电路存储单元（10）包括第一时钟线（34）和第二时钟线（36）。 第一晶体管（20）互连到位线（12）和字线（14），用于提供对存储单元（10）的访问。 第二晶体管（22）与电池电压源（26）和第一晶体管（20）互连，由此限定第一节点（S）。 第二晶体管（22）提供从单电池电压源（26）到第一节点（S）的充电路径。 提供电容器（30）并将第一时钟线（34）和第二晶体管（22）互连。 电容器（30）和第二晶体管（22）之间的互连限定第二节点（K）。 电容器（30）在第一时钟线（34）和第二节点（K）之间提供耦合路径，用于从第一时钟线（34）向第二节点（K）有条件地提供电压以在第二时钟线 （K）高于电池电压源（26）。 第三晶体管被提供给存储单元（10）并且互连到第一节点（S）和第二节点（K）和第二时钟线（36）。 第三晶体管（24）在第二时钟线（36）和第二节点（K）之间提供充电路径，用于有条件地维持第二节点（K）的电压。

公开(公告)号：US5532958A

公开(公告)日：1996-07-02

申请号：US135722

申请日：1993-11-24

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/40

CPC classification number: G06F5/065 ,  G11C11/41 ,  G11C11/412 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

公开(公告)号：USRE34241E

公开(公告)日：1993-05-04

申请号：US490801

申请日：1990-03-08

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: H04J3/06

CPC classification number: H04J3/0605

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

公开(公告)号：US5162757A

公开(公告)日：1992-11-10

申请号：US499853

申请日：1990-03-27

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03B5/36 ,  H03K3/014 ,  H03K3/354 ,  H03L3/00

CPC classification number: H03B5/06 ,  H03B5/364 ,  H03K3/014 ,  H03K3/3545 ,  H03L3/00 ,  H03B2200/0012

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during startup.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4843265A

公开(公告)日：1989-06-27

申请号：US217142

申请日：1988-06-30

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G05F1/46

CPC classification number: G05F1/466 ,  Y10S323/907

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

公开(公告)号：US4730346A

公开(公告)日：1988-03-08

申请号：US13911

申请日：1987-02-12

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: H04J3/06 ,  H04L7/08

CPC classification number: H04J3/0605

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.

Abstract translation: 通过将串行比特流的最后一位与串行比特流的预定数量的先前比特相组合来定位串行比特流中的嵌入的成帧位模式，该预定数量的串行比特流的先前比特间隔开成帧位的比特的间距 模式，并且测试这些位的组合以确定组合是否匹配成帧位模式的一部分。 如果没有发生匹配，则组合在一起的位被改变成不会导致匹配的位模式，当这些位（除了被忽略的最老位除外）被再次与串行的新位组合时 位流，无论新位的逻辑状态如何。 以这种方式，当它们到达并被组合和测试时，所有位将最终被改变，除了作为帧位模式的一部分的位之外。

公开(公告)号：US6118690A

公开(公告)日：2000-09-12

申请号：US563152

申请日：1995-11-27

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/419

CPC classification number: G06F5/065 ,  G11C11/41 ,  G11C11/412 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。