公开(公告)号：US07298176B2

公开(公告)日：2007-11-20

申请号：US11204401

申请日：2005-08-16

Applicant: Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

Inventor： Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

IPC: H03K19/20

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract translation: 动态逻辑门具有非对称双栅极PFET器件，用于在时钟的预充电阶段期间对动态节点进行充电。 逻辑树在时钟的评估阶段评估动态节点。 非对称双栅极PFET器件的前栅极耦合到时钟信号，而后栅极耦合到电源的地电位。 当时钟为逻辑0时，前门和后门都被偏置为ON，动态节点以最大电流充电。 在时钟关断前门的评估阶段，时钟信号转变为逻辑1。 背栅保持接通，并且非对称双栅极PFET器件作为具有足以抵抗动态节点上的泄漏的电流水平的保持器器件工作。

公开(公告)号：US20070047364A1

公开(公告)日：2007-03-01

申请号：US11216666

申请日：2005-08-31

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Hung Ngo ,  Kevin Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Hung Ngo ,  Kevin Nowka

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/412 ,  G11C11/417

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract translation: 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

公开(公告)号：US20070040621A1

公开(公告)日：2007-02-22

申请号：US11204412

申请日：2005-08-16

Applicant: Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.

Abstract translation: 使用由不对称双门控FET（ADG-FET）器件配置的反相级形成环形振荡器。 最简单的形式使用由ADG-PFET和ADG-NFET配置的奇数CMOS反相器级。 前门用作逻辑输入，并连接到主环的前一个输出。 ADG-PFET器件的背栅极耦合到第一控制电压，并且ADG-NFET器件的背栅极耦合到作为基于偏移电压的第一控制电压的补码的第二控制电压。 也可以使用使用ADG-FET器件的逻辑反相级的其它配置。 改变控制电压以调制由耦合到前门的输入端处的逻辑状态设置的电流电平。

公开(公告)号：US20060290383A1

公开(公告)日：2006-12-28

申请号：US11168692

申请日：2005-06-28

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K19/096

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract translation: 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

公开(公告)号：US20060232321A1

公开(公告)日：2006-10-19

申请号：US11106913

申请日：2005-04-15

Applicant: Ching-Te Chuang ,  Koushik Das ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Koushik Das ,  Keunwoo Kim

IPC: H03K17/687

CPC classification number: H01L27/105 ,  G11C5/14 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/785 ,  H01L29/78648 ,  H03K3/356156

Abstract: A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

Abstract translation: 具有强大数据保持能力的新型电源门控结构，仅使用一个单栅极器件来提供电源门控开关和虚拟电源/接地二极管钳位功能。 该方案降低了电源门控结构的晶体管数量，面积和电容，从而提高了电路性能，功率和泄漏。 该方案通过基于混合模式物理的二维数值模拟与常规电力门控结构进行比较。 还提出了拟议方案的虚拟供应/地面反弹分析。

公开(公告)号：US20060226493A1

公开(公告)日：2006-10-12

申请号：US11100883

申请日：2005-04-07

Applicant: Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

Inventor： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

IPC: H01L29/94

CPC classification number: H03K19/0016 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG

Abstract translation: 公开了结合MTCMOS和混合定向技术的CMOS电路设计，以实现高性能和低待机泄漏功率的双重目标。 本发明利用HOT技术中的厚氧化物高VTH PFET集线器的新型组合与各种栅极和体偏置方案，以显着降低与常规PFET集管相关的性能损失。 本发明的第一实施例提供了一种HOT-B高VTH厚氧化物体PFET头方案。 可以通过在待机模式期间将正栅极偏置VPOS（VPOS> VDD）施加到HOT-B PFET头并且在活动模式下使用负栅极偏置VNEG（VNEG

公开(公告)号：US08659936B2

公开(公告)日：2014-02-25

申请号：US12979345

申请日：2010-12-28

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C11/21

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

Abstract translation: 在待机模式和写入模式下，将存储单元阵列保持在低电压状态的SRAM，并在读取模式下将存储单元阵列电源电压提高到高电平。 一种SRAM，包括：至少一个存储单元电路，包括具有至少两个反相器的锁存电路，并且包括用于接收电力的两个电力接收端子; 以及供电电路，用于向存储单元电路提供电力，使得当数据被写入锁存电路时，锁存电路的电力接收端的电压低于预定的电压电平。 在一个实施例中，存储单元电路包括多个数据访问终端，并且数据访问终端分别由至少两个传输晶体管开关器件控制。

公开(公告)号：US08582378B1

公开(公告)日：2013-11-12

申请号：US13597733

申请日：2012-08-29

Applicant: Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

Inventor： Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/50004 ,  G11C11/41 ,  G11C29/12005

Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

Abstract translation: 公开了一种阈值电压测量装置。 该器件耦合到6T SRAM。 SRAM包括两个各自耦合到FET的反相器。 一个逆变器的电源端子处于浮动状态; 耦合到逆变器的FET的漏极和源极短路。 两个电压选择器，电阻，放大器和SRAM以负反馈的方式连接。 不同的偏置电压被施加到SRAM，用于测量另一个反相器的两个FET和耦合到另一个反相器的FET的阈值电压。 本发明使用单个电路来测量三个FET的阈值电压，而不改变SRAM的物理结构。 从而加快了测量并降低了制造过程和测量仪器的成本。

公开(公告)号：US20130100731A1

公开(公告)日：2013-04-25

申请号：US13419291

申请日：2012-03-13

Applicant: Ching-Te CHUANG ,  Yin-Nien Chen ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

Inventor： Ching-Te CHUANG ,  Yin-Nien Chen ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

IPC: G11C11/40

CPC classification number: G11C11/412

Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.

Abstract translation: 本发明提供了一种IG 7T FinFET SRAM，其采用独立控制的栅极超高VT FinFET来实现层叠性质，从而消除读取干扰和半选择干扰。 此外，本发明使用保持器电路和读取控制电压来减少读取期间位线的泄漏电流。 此外，本发明可以有效地克服在低操作电压下可能具有读错误的常规6T SRAM的问题。

公开(公告)号：US08325512B2

公开(公告)日：2012-12-04

申请号：US13070977

申请日：2011-03-24

Applicant: Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

Inventor： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract translation: 提供了SRAM写入系统和相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。