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    Methods of fabricating copper interconnects for integrated circuits
    11.
    发明授权
    Methods of fabricating copper interconnects for integrated circuits 失效
    制造用于集成电路的铜互连的方法

    公开(公告)号：US5899740A

    公开(公告)日：1999-05-04

    申请号：US923279

    申请日：1997-09-04

    Applicant: Chul-soon Kwon

    Inventor： Chul-soon Kwon

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/4763

    CPC classification number: H01L21/76859 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002

    Abstract: Interconnects for integrated circuit substrates are formed by forming a diffusion-barrier film on an integrated circuit substrate and amorphizing the diffusion-barrier film to create an amorphous diffusion-barrier film. A copper film is then formed on the amorphous diffusion-barrier film. Amorphizing may be performed by implanting ions into the diffusion-barrier film. The diffusion-barrier film can include Mo, W, Ti, Wn, TiW, TiN and the ions may be boron, nitrogen and silicon ions. Interconnect structures according to the invention include an amorphous conductive diffusion-barrier film on an integrated circuit substrate and a copper film on the amorphous conductive diffusion-barrier film. The amorphous conductive diffusion-barrier film preferably contains ions therein. The amorphous conductive diffusion-barrier film and the ions may be selected from materials as described above.

    Abstract translation: 用于集成电路基板的互连通过在集成电路基板上形成扩散阻挡膜并使该扩散阻挡膜非晶化以形成无定形扩散阻挡膜而形成。 然后在无定形扩散阻挡膜上形成铜膜。 可以通过将离子注入到扩散阻挡膜中来进行非晶化。 扩散阻挡膜可以包括Mo，W，Ti，Wn，TiW，TiN，离子可以是硼，氮和硅离子。 根据本发明的互连结构包括集成电路基板上的非晶导电扩散阻挡膜和非晶导电扩散阻挡膜上的铜膜。 非晶导电性扩散阻挡膜优选在其中含有离子。 非晶导电扩散阻挡膜和离子可以选自如上所述的材料。

    Flash memory device having a split gate
    13.
    发明申请
    Flash memory device having a split gate 有权
    具有分闸的闪存器件

    公开(公告)号：US20070026613A1

    公开(公告)日：2007-02-01

    申请号：US11503126

    申请日：2006-08-14

    Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    IPC: H01L21/336

    CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

    Abstract translation: 具有能够防止有源区域和浮栅电极不对准的分离栅极的闪存器件及其制造方法包括在半导体衬底上依次层叠栅极氧化物层和浮置栅极导电层，形成 在形成有浮栅导电层的半导体衬底的预定区域中形成隔离层，并限定有源区。 然后，通过在活性区域上氧化浮栅导电层的预定部分来形成局部氧化层。 通过使用局部氧化物层图案化浮栅导电层来形成浮栅电极结构。

    Split gate type flash memory device and method of manufacturing the same
    14.
    发明申请
    Split gate type flash memory device and method of manufacturing the same 审中-公开
    分体式闪存器件及其制造方法

    公开(公告)号：US20060001077A1

    公开(公告)日：2006-01-05

    申请号：US11152779

    申请日：2005-06-15

    Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    IPC: H01L29/788 ,  H01L21/8238

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    Abstract: In a split gate type flash memory device, and a method of manufacturing the same, the device includes a memory cell array having a memory cell uniquely determined by a contact of a corresponding bit line and a corresponding word line, a floating gate formed on a semiconductor substrate to constitute the memory cell, the floating gate having a horizontal surface parallel to a main surface of the substrate, a vertical surface perpendicular to the main surface of the substrate, and a curved surface extending between the horizontal and vertical surfaces, a control gate formed over the curved surface of the floating gate in an area defined by an angle range of less than 90° between an extension line of the horizontal surface and an extension line of the vertical surface, and source and drain regions formed in an active region of the substrate.

    Abstract translation: 在分闸式闪存器件及其制造方法中，该器件包括存储单元阵列，该存储单元阵列具有由对应的位线和对应的字线的接触唯一地确定的存储单元，形成在 半导体衬底以构成存储单元，浮置栅极具有平行于衬底的主表面的水平表面，垂直于衬底主表面的垂直表面以及在水平和垂直表面之间延伸的曲面，控制器 在浮动栅极的弯曲表面上形成的水平表面的延伸线和垂直表面的延伸线之间的角度范围小于90°的区域，以及形成在有源区域中的源极和漏极区域 的基底。

    Non-volatile memory device having dummy pattern
    16.
    发明授权
    Non-volatile memory device having dummy pattern 有权
    具有虚拟图案的非易失性存储器件

    公开(公告)号：US06853028B2

    公开(公告)日：2005-02-08

    申请号：US10619998

    申请日：2003-07-14

    Applicant: Yong-Hee Kim ,  Chul-Soon Kwon ,  Jin-Woo Kim

    Inventor： Yong-Hee Kim ,  Chul-Soon Kwon ,  Jin-Woo Kim

    IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11531

    Abstract: A non-volatile memory device includes a cell region and a peripheral circuit region at the semiconductor substrate. A plurality active regions are disposed in the cell region in parallel with each other. A plurality of cell line patterns cross over the active regions in parallel. A couple of tunnel insulating layers and the floating gate electrodes are disposed between the cell line patterns and the active regions. A dummy region is interposed between the cell region and the peripheral circuit region where at least one dummy line pattern is disposed in the dummy region.

    Abstract translation: 非易失性存储器件包括在半导体衬底处的单元区域和外围电路区域。 多个有源区域彼此平行地设置在单元区域中。 多个细胞系图案平行地跨越有源区域。 一对隧道绝缘层和浮栅电极设置在细胞线图案和有源区之间。 在单元区域和外围电路区域之间插入虚拟区域，其中在虚拟区域中设置至少一个虚拟线图案。

    Nonvolatile memory device and method for manufacturing the same
    17.
    发明申请
    Nonvolatile memory device and method for manufacturing the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20070252190A1

    公开(公告)日：2007-11-01

    申请号：US11653962

    申请日：2007-01-17

    Applicant: Jae-Hyun Park ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Ji-Woon Rim ,  Young-Cheon Jeong ,  In-Gu Yoon ,  Jung-Ho Moon

    Inventor： Jae-Hyun Park ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Ji-Woon Rim ,  Young-Cheon Jeong ,  In-Gu Yoon ,  Jung-Ho Moon

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    Abstract: Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a third insulation layer, a control gate, and a common source line. The semiconductor substrate may have an active region limited by a device isolation region. The floating gate may be formed on the active region with a first insulation layer between the floating gate and the active region. The second insulation layer covers one side of the floating gate, and the third insulation layer covers the floating gate and the second insulation layer. The control gate may be formed on the other side of the floating gate with a fourth insulation layer between the control gate and the floating gate. The common source line may be formed in a portion of the substrate that is located under the second insulation layer.

    Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括半导体衬底，浮置栅极，第二绝缘层，第三绝缘层，控制栅极和公共源极线。 半导体衬底可以具有被器件隔离区限制的有源区。 浮置栅极可以在有源区上形成在浮置栅极和有源区域之间的第一绝缘层。 第二绝缘层覆盖浮栅的一侧，第三绝缘层覆盖浮栅和第二绝缘层。 控制栅极可以在浮动栅极的另一侧上形成在控制栅极和浮动栅极之间的第四绝缘层。 公共源极线可以形成在位于第二绝缘层下方的衬底的一部分中。

    NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    18.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20070170490A1

    公开(公告)日：2007-07-26

    申请号：US11624464

    申请日：2007-01-18

    Applicant: Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

    Inventor： Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

    IPC: H01L29/788 ,  H01L21/8238

    CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be elecrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

    Abstract translation: 非易失性存储器件包括半导体衬底; 源区域，其形成在所述半导体衬底中; 形成为与半导体衬底上的源极区域重叠的栅极绝缘膜; 形成在所述栅极绝缘膜上的浮栅，以具有在与所述源极区重叠的部分中形成均匀电场的结构; 形成为从浮置栅极的上部的浮动栅极的一个侧壁电隔离的控制栅极，插入在浮置栅极和控制栅极之间的栅极间绝缘膜，以及漏极区域 其形成为与控制栅极的另一侧相邻。

    Flash memory device having a split gate and method of manufacturing the same
    20.
    发明申请
    Flash memory device having a split gate and method of manufacturing the same 有权
    具有分裂栅的闪存器件及其制造方法

    公开(公告)号：US20050250282A1

    公开(公告)日：2005-11-10

    申请号：US11119801

    申请日：2005-05-03

    Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

    Abstract translation: 具有能够防止有源区域和浮栅电极不对准的分离栅极的闪存器件及其制造方法包括在半导体衬底上依次层叠栅极氧化物层和浮置栅极导电层，形成 在形成有浮栅导电层的半导体衬底的预定区域中形成隔离层，并限定有源区。 然后，通过在活性区域上氧化浮栅导电层的预定部分来形成局部氧化层。 通过使用局部氧化物层图案化浮栅导电层来形成浮栅电极结构。

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