公开(公告)号：US06268639B1

公开(公告)日：2001-07-31

申请号：US09248547

申请日：1999-02-11

Applicant: Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

Inventor： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

IPC: H01L218222

CPC classification number: H01L27/0251 ,  Y10S438/983

Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

Abstract translation: ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。 电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。 齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。 如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。 齐纳二极管包括阳极和阴极扩散。 阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。 阳极扩散通过阴极扩散向下延伸到半导体衬底中。 阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。 可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

公开(公告)号：US07688639B1

公开(公告)日：2010-03-30

申请号：US11974361

申请日：2007-10-12

Applicant: Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

IPC: G11C16/06

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US20090108337A1

公开(公告)日：2009-04-30

申请号：US11977810

申请日：2007-10-26

Applicant: Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak Kumar Nayak ,  Daniel Gitlin

Inventor： Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak Kumar Nayak ,  Daniel Gitlin

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/0251

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract translation: 公开了一种保护形成在集成电路的管芯上的晶体管的方法。 该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。 还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

公开(公告)号：US07032194B1

公开(公告)日：2006-04-18

申请号：US10369888

申请日：2003-02-19

Applicant: Shih-Cheng Hsueh ,  Xiao-Jie Yuan ,  Daniel Gitlin

Inventor： Shih-Cheng Hsueh ,  Xiao-Jie Yuan ,  Daniel Gitlin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

Abstract translation: 处理过程特定物理效应的方法对IC布局进行尺寸修改以补偿由物理效应引起的性能变化。 由于尺寸修改使实际IC的性能与IC型号的性能相协调，因此不需要耗时的重新验证操作。 由浅沟槽隔离（STI）应力引起的电流驱动变化可以通过调整受影响的晶体管的栅极尺寸以根据需要增加或减少电流驱动来补偿。 这种物理效应补偿可以在光学邻近校正（OPC）之前，之后或甚至同时应用。 用于物理效应补偿的尺寸修改也可以并入到OPC引擎中。

公开(公告)号：US06645802B1

公开(公告)日：2003-11-11

申请号：US09877690

申请日：2001-06-08

Applicant: Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

Inventor： Sheau-Suey Li ,  Shahin Toutounchi ,  Michael J. Hart ,  Xin X. Wu ,  Daniel Gitlin

IPC: H01L218234

CPC classification number: H01L27/0251 ,  Y10S438/983

Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

Abstract translation: ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。 电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。 齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。 如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。 齐纳二极管包括阳极和阴极扩散。 阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。 阳极扩散通过阴极扩散向下延伸到半导体衬底中。 阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。 可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

公开(公告)号：US07956385B1

公开(公告)日：2011-06-07

申请号：US12847957

申请日：2010-07-30

Applicant: Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak K. Nayak ,  Daniel Gitlin

Inventor： Yuhao Luo ,  Shuxian Wu ,  Xin X. Wu ,  Jae-Gyung Ahn ,  Deepak K. Nayak ,  Daniel Gitlin

IPC: H01L23/525

CPC classification number: H01L27/0251

Abstract: A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Abstract translation: 公开了一种用于在制造集成电路器件期间保护晶体管的电路。 该电路包括晶体管，其晶体管具有形成在集成电路器件的管芯中的有源区上的栅极; 形成在集成电路器件的管芯中的保护元件; 以及耦合在所述晶体管的栅极和所述保护元件之间的可编程互连，所述可编程互连使得所述保护元件能够与所述晶体管分离。

公开(公告)号：US07687797B1

公开(公告)日：2010-03-30

申请号：US11210500

申请日：2005-08-24

Applicant: James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

Inventor： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

IPC: H01L29/06 ,  H01L47/02

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Abstract translation: MOS晶体管用作可编程三端非易失性存储元件。 MOS晶体管的栅介质层具有比第二部分具有相对更高的介电击穿强度的第一部分。 选择第二部分的位置以避免在编程期间栅极电介质层在有源区域或隔离区域的边缘附近分解。 在特定实施例中，栅介质层是氧化硅，第一部分比第二部分厚。

公开(公告)号：US06549458B1

公开(公告)日：2003-04-15

申请号：US10040044

申请日：2001-10-25

Applicant: Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

Inventor： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC: G11C1400

CPC classification number: G11C16/08

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract translation: 用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。 有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

公开(公告)号：US06522582B1

公开(公告)日：2003-02-18

申请号：US09553571

申请日：2000-04-19

Applicant: Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

Inventor： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC: G11C1400

CPC classification number: G11C16/08

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

Abstract translation: 描述了用于非易失性存储器件的存储单元结构和相关电路。 可以使用标准CMOS工艺制造电池结构，例如 次0.35微米或次级0.25微米工艺。 优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。 有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。 例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径 型源极/漏极区域。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。 此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。 这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

公开(公告)号：US06266269B1

公开(公告)日：2001-07-24

申请号：US09589337

申请日：2000-06-07

Applicant: James Karp ,  Daniel Gitlin ,  Shahin Toutounchi

Inventor： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi

IPC: G11C1124

CPC classification number: G11C16/0466

Abstract: A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.

Abstract translation: 三端非易失性存储元件包括标准（低电压）CMOS晶体管，即存储晶体管，其具有耦合到读位线的漏极和连接到地的源极。 存储晶体管通过向其栅极施加高编程电压来编程，从而破坏存储晶体管的栅极氧化物。 重要的是，在亚微米技术中，存储晶体管的源极和漏极区域合并，从而提供高度可靠的导电路径。 因此，存储单元的状态可以有利地仅通过读位线读取。