公开(公告)号：US20050128854A1

公开(公告)日：2005-06-16

申请号：US11047025

申请日：2005-01-31

Applicant: Gil Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

Inventor： Gil Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

IPC: G06F13/40 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/00 ,  G11C8/10 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.

Abstract translation: 本发明涉及同步自定时存储装置。 该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。 本地感测放大器至少与解码器和单元阵列接口，并且适于对与其耦合的至少一条线进行预充电和均衡。 本地控制器与至少本地解码器和读出放大器的活动接口并进行协调。

公开(公告)号：US20050122805A1

公开(公告)日：2005-06-09

申请号：US11041829

申请日：2005-01-24

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: G11C29/50 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/2602

Abstract: The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic I is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

Abstract translation: 本发明涉及并行地应用分层存储器结构的系统和方法，测试弱缺陷的存储器结构。 本发明包括将逻辑0写入到存储器结构中的所有存储单元中。 所有高地址预编码线路和最低地址的交替预编码线路都被使能。 相邻字线和位线之间的电压降受到影响。 逻辑I被写入存储器结构中的所有存储器单元。 由于存储器单元中的逻辑1，在位线上产生相反的电压极性。 通过翻转最低预编码行的状态（即，通过改变对应于该行的输入地址），在字线上实现反向电压极性应力。

公开(公告)号：US07759970B2

公开(公告)日：2010-07-20

申请号：US12464629

申请日：2009-05-12

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件元件的可编程保险丝与多个存储器单元一起被使用以指示至少一个存储器单元不可用并且应该被移出而不工作。 软件可编程元件包括可编程寄存器，其适于移位指示至少一个存储器单元有缺陷的适当值。 硬件元件包括一个带可编程寄存器的保险丝。 移位由软件可编程保险丝或硬保险丝指示。 软熔丝寄存器可以链接在一起形成移位寄存器。

公开(公告)号：US07532031B2

公开(公告)日：2009-05-12

申请号：US12122932

申请日：2008-05-19

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

公开(公告)号：US20070165435A1

公开(公告)日：2007-07-19

申请号：US11431439

申请日：2006-05-10

Applicant: Gil Winograd ,  Esin Terzioglu ,  Morteza Afghahi

Inventor： Gil Winograd ,  Esin Terzioglu ,  Morteza Afghahi

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

Abstract translation: 在一个实施例中，提供了一种CAM，其包括： 分组存储单词的多个存储单元，其中所述存储单元组织成多个纹波组，每个纹波组包括复合逻辑门，其配置用于确定所述纹波组的存储单元的存储内容是否与 一个比较字，如果纹波组的使能输入被断言，则每个复合逻辑门在该确定指示匹配时将输出置为有效，波纹组从第一纹波组布置到最后纹波组，使得来自第一 纹波组的复杂逻辑门用作第二纹波组的复杂逻辑门等的使能输入，使得来自下一个到最后纹波组的复杂逻辑门的输出用作最后纹波组的复杂逻辑门的使能输入 。

公开(公告)号：US20050259501A1

公开(公告)日：2005-11-24

申请号：US11191803

申请日：2005-07-28

Applicant: Ali Anvar ,  Gil Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil Winograd ,  Esin Terzioglu

IPC: G06F13/40 ,  G11C5/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/00 ,  G11C8/10 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

公开(公告)号：US20050111277A1

公开(公告)日：2005-05-26

申请号：US11024560

申请日：2004-12-29

Applicant: Zeynep Toros ,  Esin Terzioglu ,  Ahmad Siksek ,  Gil Winograd ,  Ali Anvar

Inventor： Zeynep Toros ,  Esin Terzioglu ,  Ahmad Siksek ,  Gil Winograd ,  Ali Anvar

IPC: G11C16/12 ,  G11C7/02

CPC classification number: G11C16/12

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) and a controller (90). The controller is arranged to store a predetermined logical value in the cell by generating a series of the operating voltages beginning with the first voltage and continuing with successively larger operating voltages greater the first voltage. The voltages are transmitted to the cell from the voltage generator. After each transmittal of one of the series of operating voltages, the controller causes at least a portion of the charge stored in the cell to flow in the bit line. The controller determines whether the predetermined one of the logical values has been stored in the cell in response to the flow of charge. The controller terminates transmittal of the series of operating voltages to the cell in the event that the predetermined one of the logical states has been stored or in the event that one of the series of successively larger operating voltages equals the second voltage.

Abstract translation: 数字存储器系统（30）包括存储单元（10），位线（12），电压发生器（320）和控制器（90）。 控制器被布置为通过产生从第一电压开始的一系列操作电压并且继续连续地更大的第一电压的工作电压来在电池中存储预定的逻辑值。 电压从电压发生器传输到电池。 在每个传送一系列工作电压之一之后，控制器使存储在单元中的电荷的至少一部分流入位线。 控制器响应于电荷流动来确定逻辑值中的预定的一个是否已经存储在该单元中。 在已经存储了预定的一个逻辑状态的情况下或者在连续较大的一连串操作电压中的一个等于第二电压的情况下，控制器终止该单元的一系列工作电压的传送。

公开(公告)号：US20050030831A1

公开(公告)日：2005-02-10

申请号：US10939679

申请日：2004-09-13

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: G11C29/00 ,  G11C11/34

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software modes, is used with the plurality of memory cells to indicate that at least one memory cells is unusable and should be shifted out of operation. The software mode comprises a software programmable element adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware mode comprises a hardware element adapted to indicate the at least one memory cell is unusable and is gated with the software programmable element. The hardware and software modes act autonomously

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件模式的可编程保险丝与多个存储器单元一起使用以指示至少一个存储器单元不可用并且应该被移出运行。 软件模式包括适于移动指示至少一个存储器单元有缺陷的适当值的软件可编程元件。 硬件模式包括适于指示至少一个存储器单元不可用并且被软件可编程元件选通的硬件元件。 硬件和软件模式自动运行

公开(公告)号：US20070297266A1

公开(公告)日：2007-12-27

申请号：US11766200

申请日：2007-06-21

Applicant: Ali Anvar ,  Gil Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil Winograd ,  Esin Terzioglu

IPC: G11C8/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。

公开(公告)号：US20060027733A1

公开(公告)日：2006-02-09

申请号：US11194580

申请日：2005-08-02

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: H01L27/00

CPC classification number: H04N5/361

Abstract: The present invention includes an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. In embodiments, the active pixel sensor can be implemented in a standard CMOS process, without the need for a specialized optical process. The active pixel sensor includes a reset FET, a photo-diode, a source follower, and a current source. The photo-diode is coupled to the source of the reset FET at a discharge node. The drain of the reset FET is couple to a power supply VDD. The discharge node is also coupled to the gate input of the source follower, the output of which is coupled to output node. In embodiments, shallow trench isolation is inserted between the active devices that constitute the photo-diode, the source follower, or the current source, where the shallow trench isolation reduces leakage current between these devices. As a result, dark current is reduced and overall sensitivity is improved. This enables the active pixel sensor to be integrated on a single substrate fabricated with conventional CMOS processing.

Abstract translation: 本发明包括有源像素传感器，其检测光能并产生与光能成比例的模拟输出。 在实施例中，有源像素传感器可以在标准CMOS工艺中实现，而不需要专门的光学工艺。 有源像素传感器包括复位FET，光电二极管，源极跟随器和电流源。 光电二极管在放电节点耦合到复位FET的源极。 复位FET的漏极耦合到电源VDD。 放电节点还耦合到源极跟随器的栅极输入，其输出耦合到输出节点。 在实施例中，浅沟槽隔离被插入在构成光电二极管，源极跟随器或电流源的有源器件之间，其中浅沟槽隔离减少了这些器件之间的漏电流。 结果，暗电流降低，整体灵敏度提高。 这使得有源像素传感器能够集成在用常规CMOS处理制造的单个衬底上。