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    DRAM based refresh-free ternary CAM
    11.
    发明授权
    DRAM based refresh-free ternary CAM 有权
    基于DRAM的无刷新三元CAM

    公开(公告)号：US06331961B1

    公开(公告)日：2001-12-18

    申请号：US09591033

    申请日：2000-06-09

    申请人： Subramani Kengeri ,  Hemraj K. Hingarh

    发明人： Subramani Kengeri ,  Hemraj K. Hingarh

    IPC分类号： G11C700

    CPC分类号： G11C11/406 ,  G11C15/043

    摘要： A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.

    摘要翻译： 包含两个DRAM单元的三态状态内容可寻址存储器（CAM）单元。 除了用于控制和发送数据到CAM的端口之外，另一个端口专门用于刷新DRAM单元。 刷新字线耦合到两个DRAM单元用于执行DRAW单元刷新。 刷新位线耦合到两个DRAM单元中的第一个用于刷新该第一DRAM单元。 刷新位线耦合到两个DRAM单元中的第二个用于刷新该第二DRAM单元。 在CAM中克服了传统CAM中出现的有问题的功耗和电压摆动。 摆动线（SL）耦合到所述第一和第二DRAM单元和所述CAM单元的局部匹配线（LML），所述SL具有用于改变所述LML中的电压摆幅的可调节电压电平，以调节功率消耗之间的权衡 和所述CAM单元的速度。

    Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design
    14.
    发明授权
    Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design 失效
    集成注入逻辑和晶体管晶体管逻辑微处理器集成电路设计

    公开(公告)号：US4396980A

    公开(公告)日：1983-08-02

    申请号：US167614

    申请日：1980-07-11

    申请人： Hemraj K. Hingarh

    发明人： Hemraj K. Hingarh

    IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F15/78 ,  H01L27/02 ,  H03K3/288 ,  H03K3/289 ,  H03K19/018 ,  G06F3/00 ,  G06F7/48

    CPC分类号： G06F9/30 ,  H01L27/0233 ,  H03K19/01818 ,  H03K3/288 ,  H03K3/289

    摘要： A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I.sup.2 L) and transistor-transistor logic (T.sup.2 L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T.sup.2 - I.sup.2 L interface circuit and structure supplies a T.sup.2 L input to a plurality of I.sup.2 L input stages, each having a restricted cross-sectional area resistor element in the base of an I.sup.2 L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I.sup.2 L clocking pulse input transistors in a T.sup.2 L master-slave circuit avoids capacitive coupling problems and allows the master-slave circuit to operate over a much wider temperature range. A cycle counter for the micro-processor integrated circuit implemented as an improved ripple down counter requires a minimum number of gates while avoiding significant delay in operation.

    摘要翻译： 微处理器集成电路设计改进了集成电路中集成注入逻辑（I2L）和晶体管晶体管逻辑（T2L）之间的分区。 包含双向输入和输出缓冲器和双向输入和输出多路复用器的信息总线结构使集成电路中的内部总线线路数量最少化。 改进的T2-I2L接口电路和结构将T2L输入提供给多个I2L输入级，每个I2L输入级在I2L输入晶体管的基极中具有受限制的横截面积的电阻元件。 集成电路中的存储寄存器具有设置在寄存器的每个触发器电路处的复用器部分。 在速度至关重要的集成电路的寄存器中采用高速前馈触发器电路。 可编程逻辑阵列（PLA）中改进的电压调节器和电流源组合降低了PLA的温度灵敏度。 T2L主从电路中的一对I2L时钟脉冲输入晶体管避免了电容耦合问题，并允许主从电路在更宽的温度范围内工作。 实现为改进的纹波衰减计数器的微处理器集成电路的周期计数器需要最小数量的门，同时避免操作中的显着延迟。